mirror of https://github.com/YosysHQ/yosys.git
137 lines
2.4 KiB
Verilog
137 lines
2.4 KiB
Verilog
module IBUF(input I, output O);
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assign O = I;
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endmodule
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module IOBUFE(input I, input E, output O, inout IO);
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assign O = IO;
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assign IO = E ? I : 1'bz;
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endmodule
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module ANDTERM(IN, IN_B, OUT);
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parameter TRUE_INP = 0;
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parameter COMP_INP = 0;
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input [TRUE_INP-1:0] IN;
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input [COMP_INP-1:0] IN_B;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 1;
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for (i = 0; i < TRUE_INP; i=i+1)
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OUT = OUT & IN[i];
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for (i = 0; i < COMP_INP; i=i+1)
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OUT = OUT & ~IN_B[i];
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end
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endmodule
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module ORTERM(IN, OUT);
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parameter WIDTH = 0;
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input [WIDTH-1:0] IN;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 0;
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for (i = 0; i < WIDTH; i=i+1) begin
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OUT = OUT | IN[i];
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end
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end
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endmodule
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module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
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parameter INVERT_OUT = 0;
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input IN_PTC;
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input IN_ORTERM;
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output wire OUT;
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wire xor_intermed;
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assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
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assign xor_intermed = IN_ORTERM ^ IN_PTC;
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endmodule
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module FDCP (C, PRE, CLR, D, Q);
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parameter INIT = 0;
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input C, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @(posedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q <= 0;
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else if (PRE == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module FDCP_N (C, PRE, CLR, D, Q);
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parameter INIT = 0;
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input C, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @(negedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q <= 0;
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else if (PRE == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module LDCP (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 1)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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module LDCP_N (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 0)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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