Added ice40 test_arith

techlibs/ice40/tests/test_arith.v

@@ -0,0 +1,3 @@
+module test(input [4:0] a, b, c, output [4:0] y);
+	assign y = ((a+b) ^ (a-c)) - ((a*b) + (a*c) - (b*c));
+endmodule

techlibs/ice40/tests/test_arith.ys

@@ -0,0 +1,10 @@
+read_verilog test_arith.v
+synth_ice40
+techmap -map ../cells_sim.v
+rename test gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter