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Added techlibs/common/pmux2mux.v

This commit is contained in:
Clifford Wolf 2014-01-17 20:06:15 +01:00
parent 6170cfe9cd
commit db9cf544b8
2 changed files with 26 additions and 1 deletions
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6
techlibs/common/Makefile.inc
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@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
share/simlib.v: techlibs/common/simlib.v
mkdir -p share
@ -19,3 +19,7 @@ share/blackbox.v: techlibs/common/blackbox.v
mkdir -p share
cp techlibs/common/blackbox.v share/blackbox.v
share/pmux2mux.v: techlibs/common/pmux2mux.v
mkdir -p share
cp techlibs/common/pmux2mux.v share/pmux2mux.v

21
techlibs/common/pmux2mux.v Normal file
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@ -0,0 +1,21 @@
module \$pmux (A, B, S, Y);
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output reg [WIDTH-1:0] Y;
integer i;
always @* begin
Y <= A;
for (i = 0; i < S_WIDTH; i=i+1)
if (S[i]) Y <= B[WIDTH*i +: WIDTH];
end
endmodule