mirror of https://github.com/YosysHQ/yosys.git
Fixed assertion failure for non-inferrable counters in some cases
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@ -248,8 +248,12 @@ void greenpak4_counters_worker(
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if (cell->type != "$alu")
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return;
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//A input is the count value. Check if it has COUNT_EXTRACT set
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RTLIL::Wire* a_wire = sigmap(cell->getPort("\\A")).as_wire();
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//A input is the count value. Check if it has COUNT_EXTRACT set.
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//If it's not a wire, don't even try
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auto port = sigmap(cell->getPort("\\A"));
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if(!port.is_wire())
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return;
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RTLIL::Wire* a_wire = port.as_wire();
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bool force_extract = false;
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bool never_extract = false;
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string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();
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