mirror of https://github.com/YosysHQ/yosys.git
Added spice testbench to techlibs/cmos
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@ -165,9 +165,6 @@ struct SpiceBackend : public Backend {
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fprintf(f, "* SPICE netlist, generated by Yosys *\n");
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fprintf(f, "*************************************\n");
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fprintf(f, "\n");
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fprintf(f, ".GLOBAL %s\n", neg.c_str());
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fprintf(f, ".GLOBAL %s\n", pos.c_str());
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fprintf(f, "\n");
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for (auto module_it : design->modules)
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{
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@ -0,0 +1,34 @@
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.SUBCKT NOT A Y
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M1 Y A Vdd Vdd cmosp L=1u W=10u
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M2 Y A Vss Vss cmosn L=1u W=10u
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.ENDS NOT
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.SUBCKT NAND A B Y
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M1 Y A Vdd Vdd cmosp L=1u W=10u
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M2 Y B Vdd Vdd cmosp L=1u W=10u
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M3 Y A M34 Vss cmosn L=1u W=10u
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M4 M34 B Vss Vss cmosn L=1u W=10u
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.ENDS NAND
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.SUBCKT NOR A B Y
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M1 Y A M12 Vdd cmosp L=1u W=10u
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M2 M12 B Vdd Vdd cmosp L=1u W=10u
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M3 Y A Vss Vss cmosn L=1u W=10u
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M4 Y B Vss Vss cmosn L=1u W=10u
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.ENDS NOR
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.SUBCKT DLATCH E D Q
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X1 D E S NAND
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X2 nD E R NAND
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X3 S nQ Q NAND
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X4 Q R nQ NAND
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X5 D nD NOT
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.ENDS DLATCH
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.SUBCKT DFF C D Q
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X1 nC D t DLATCH
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X2 C t Q DLATCH
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X3 C nC NOT
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.ENDS DFF
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@ -1,12 +1,12 @@
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module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [3:0] count;
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output reg [2:0] count;
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always @(posedge clk)
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if (rst)
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count <= 4'd0;
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count <= 3'd0;
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else if (en)
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count <= count + 4'd1;
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count <= count + 3'd1;
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endmodule
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@ -0,0 +1,7 @@
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#!/bin/bash
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set -ex
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../../yosys counter.ys
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ngspice testbench.sp
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@ -0,0 +1,29 @@
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* supply voltages
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.global Vss Vdd
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Vss Vss 0 DC 0
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Vdd Vdd 0 DC 3
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* simple transistor model
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.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
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.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
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* load design and library
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.include synth.sp
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.include cmos_cells.sp
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* input signals
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Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
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Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
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Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
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Xuut clk rst en out0 out1 out2 COUNTER
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.tran 0.01 50
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.control
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run
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plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
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.endc
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.end
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