riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.

This commit is contained in:
Andrew Zonenberg 2016-12-05 21:22:41 -08:00
parent e6ab00d419
commit 981f014301
2 changed files with 120 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
techlibs/greenpak4/cells_map.v
View File

@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ);
);
endmodule
module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSR #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nSET),
.Q(Q)
);
endmodule
module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSR #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nRST),
.Q(Q)
);
endmodule
module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSRI #(
.INIT(INIT),
.SRMODE(1'b1),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nSET),
.nQ(nQ)
);
endmodule
module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DLATCHSRI #(
.INIT(INIT),
.SRMODE(1'b0),
) _TECHMAP_REPLACE_ (
.D(D),
.nCLK(nCLK),
.nSR(nRST),
.nQ(nQ)
);
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
GP_IOBUF _TECHMAP_REPLACE_ (
.IN(IN),

68
techlibs/greenpak4/cells_sim.v
View File

@ -240,6 +240,74 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
end
endmodule
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b1;
else if(!nCLK)
Q <= ~D;
end
endmodule
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b0;
else if(!nCLK)
Q <= ~D;
end
endmodule
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= ~SRMODE;
else if(!nCLK)
Q <= ~D;
end
endmodule
module GP_EDGEDET(input IN, output reg OUT);
parameter EDGE_DIRECTION = "RISING";