mirror of https://github.com/YosysHQ/yosys.git
Added simple xilinx7 technology mapping files
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module \$_DFF_P_ (D, C, Q);
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input D, C;
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output Q;
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FDRE fpga_dff (
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.D(D), .Q(Q), .C(C),
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.CE(1'b1), .R(1'b0)
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);
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endmodule
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module \$lut (I, O);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] I;
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output O;
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generate
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if (WIDTH == 1) begin:lut1
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LUT1 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]));
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end else
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if (WIDTH == 2) begin:lut2
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LUT2 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]), .I1(I[1]));
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end else
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if (WIDTH == 3) begin:lut3
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LUT3 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]), .I1(I[1]), .I2(I[2]));
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end else
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if (WIDTH == 4) begin:lut4
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LUT4 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]), .I1(I[1]), .I2(I[2]),
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.I3(I[3]));
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end else
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if (WIDTH == 5) begin:lut5
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LUT5 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]), .I1(I[1]), .I2(I[2]),
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.I3(I[3]), .I4(I[4]));
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end else
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if (WIDTH == 6) begin:lut6
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LUT6 #(.INIT(LUT)) fpga_lut (.O(O),
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.I0(I[0]), .I1(I[1]), .I2(I[2]),
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.I3(I[3]), .I4(I[4]), .I5(I[5]));
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end else begin:error
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wire TECHMAP_FAIL;
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end
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endgenerate
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endmodule
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module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [3:0] count;
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always @(posedge clk)
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if (rst)
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count <= 4'd0;
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else if (en)
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count <= count + 4'd1;
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endmodule
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@ -0,0 +1,61 @@
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk, en, rst;
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wire [3:0] count;
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counter uut_counter(
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.clk(clk),
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.count(count),
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.en(en),
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.rst(rst)
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);
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initial begin
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clk <= 0;
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forever begin
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#50;
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clk <= ~clk;
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end
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end
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initial begin
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@(posedge clk);
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forever begin
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@(posedge clk);
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$display("%d", count);
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end
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end
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initial begin
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 1; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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$finish;
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end
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endmodule
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@ -0,0 +1,41 @@
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#!/bin/bash
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set -ex
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XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
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../../yosys - <<- EOT
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# read design
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read_verilog counter.v
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# high-level synthesis
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hierarchy -check -top counter
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proc; opt; fsm; opt; techmap; opt
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# mapping logic to LUTs using Berkeley ABC
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abc -lut 6; opt
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# map internal cells to FPGA cells
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techmap -map cells.v; opt
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# write netlist
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write_verilog -noattr testbench_synth.v
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EOT
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iverilog -o testbench_gold counter_tb.v counter.v
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iverilog -o testbench_gate counter_tb.v testbench_synth.v \
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$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
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./testbench_gold > testbench_gold.txt
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./testbench_gate > testbench_gate.txt
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if diff -u testbench_gold.txt testbench_gate.txt; then
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set +x; echo; echo; banner " PASS "
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else
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exit 1
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fi
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if [ "$*" = "-clean" ]; then
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rm -f testbench_{synth.v,{gold,gate}{,.txt}}
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fi
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