riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

More explicit integer output in verilog backend

This commit is contained in:
Clifford Wolf 2013-08-22 20:22:19 +02:00
parent 4f4cb2307f
commit 39ee561169
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
backends/verilog/verilog_backend.cc
View File

@ -155,7 +155,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
width = data.bits.size() - offset;
if (data.str.empty() || width != (int)data.bits.size()) {
if (width == 32 && !no_decimal) {
uint32_t val = 0;
int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) {
assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
@ -163,7 +163,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
if (data.bits[i] == RTLIL::S1)
val |= 1 << (i - offset);
}
fprintf(f, "%d", (int)val);
fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val));
} else {
dump_bits:
fprintf(f, "%d'b", width);