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More changes to techlibs/common/simlib.v for LEC

This commit is contained in:
Clifford Wolf 2014-01-31 11:21:29 +01:00
parent 36a808c572
commit ed8ad99960
1 changed files with 11 additions and 6 deletions
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17
techlibs/common/simlib.v
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@ -1124,14 +1124,19 @@ task tr_fetch;
endtask
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst)
if (pos_arst) begin
state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
else
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end else begin
state_tmp = next_state;
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end
end
always @(state, CTRL_IN) begin