mirror of https://github.com/YosysHQ/yosys.git
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
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@ -26,7 +26,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void run_ice40_opts(Module *module)
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static void run_ice40_opts(Module *module, bool unlut_mode)
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{
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pool<SigBit> optimized_co;
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vector<Cell*> sb_lut_cells;
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@ -84,6 +84,9 @@ static void run_ice40_opts(Module *module)
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inbits.append(cell->getPort("\\I3"));
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sigmap.apply(inbits);
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if (unlut_mode)
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goto remap_lut;
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if (optimized_co.count(inbits[0])) goto remap_lut;
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if (optimized_co.count(inbits[1])) goto remap_lut;
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if (optimized_co.count(inbits[2])) goto remap_lut;
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@ -101,7 +104,7 @@ static void run_ice40_opts(Module *module)
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cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
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cell->unsetParam("\\LUT_INIT");
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cell->setPort("\\A", SigSpec({cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\I3")}));
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cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")}));
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cell->setPort("\\Y", cell->getPort("\\O"));
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I1");
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@ -133,10 +136,15 @@ struct Ice40OptPass : public Pass {
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log(" opt_clean\n");
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log(" while <changed design>\n");
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log("\n");
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log("When called with the option -unlut, this command will transform all already\n");
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log("mapped SB_LUT4 cells back to logic.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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string opt_expr_args = "-mux_undef -undriven";
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bool unlut_mode = false;
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log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
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log_push();
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@ -146,6 +154,10 @@ struct Ice40OptPass : public Pass {
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opt_expr_args += " -full";
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continue;
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}
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if (args[argidx] == "-unlut") {
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unlut_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -156,7 +168,7 @@ struct Ice40OptPass : public Pass {
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log_header(design, "Running ICE40 specific optimizations.\n");
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for (auto module : design->selected_modules())
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run_ice40_opts(module);
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run_ice40_opts(module, unlut_mode);
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Pass::call(design, "opt_expr " + opt_expr_args);
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Pass::call(design, "opt_merge");
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