mirror of https://github.com/YosysHQ/yosys.git
Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.
This commit is contained in:
Andrew Zonenberg
parent
4504dd78e9
commit
4da1a327c0
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@ -5,43 +5,6 @@
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//Cells still in this file have INCOMPLETE simulation models, need to finish them
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
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parameter PWRDN_SYNC = 1'b0;
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parameter CLK_EDGE = "RISING";
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@ -30,6 +30,292 @@ module GP_CLKBUF(input wire IN, output wire OUT);
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assign OUT = IN;
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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reg[13:0] count = COUNT_TO;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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OUT <= (count == 14'h0);
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK or posedge RST) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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if(RST)
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count <= 0;
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end
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end
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"FALLING": begin
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always @(posedge CLK or negedge RST) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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if(!RST)
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count <= 0;
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT8 not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT8");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT <= (count == 14'h4000);
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else
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OUT <= (count == 14'h0);
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POUT <= count[7:0];
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK or posedge RST) begin
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//Main counter
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if(KEEP) begin
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end
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else if(UP)
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count <= count + 1'd1;
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else
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count <= count - 1'd1;
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//Wrapping
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if(count == 0 && !UP)
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count <= COUNT_TO;
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if(count == 14'h4000 && UP)
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count <= COUNT_TO;
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK or negedge RST) begin
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//Main counter
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if(KEEP) begin
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end
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else if(UP)
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count <= count + 1'd1;
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else
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count <= count - 1'd1;
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//Wrapping
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if(count == 0 && !UP)
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count <= COUNT_TO;
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if(count == 14'h4000 && UP)
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count <= COUNT_TO;
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT14_ADV");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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input UP, input KEEP, output reg[7:0] POUT);
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parameter RESET_MODE = "RISING";
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parameter RESET_VALUE = "ZERO";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT <= (count == 8'hff);
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else
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OUT <= (count == 8'h0);
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POUT <= count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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generate
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case(RESET_MODE)
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"RISING": begin
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always @(posedge CLK or posedge RST) begin
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//Main counter
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if(KEEP) begin
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end
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else if(UP)
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count <= count + 1'd1;
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else
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count <= count - 1'd1;
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//Wrapping
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if(count == 0 && !UP)
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count <= COUNT_TO;
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if(count == 8'hff && UP)
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count <= COUNT_TO;
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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end
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end
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"FALLING": begin
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always @(posedge CLK or negedge RST) begin
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//Main counter
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if(KEEP) begin
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end
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else if(UP)
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count <= count + 1'd1;
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else
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count <= count - 1'd1;
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//Wrapping
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if(count == 0 && !UP)
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count <= COUNT_TO;
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if(count == 8'hff && UP)
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count <= COUNT_TO;
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//Resets
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if(RST) begin
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if(RESET_VALUE == "ZERO")
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count <= 0;
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else
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count <= COUNT_TO;
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end
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end
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end
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"BOTH": begin
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initial begin
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$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
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$finish;
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end
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end
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"LEVEL": begin
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end
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default: begin
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initial begin
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$display("Invalid RESET_MODE on GP_COUNT8_ADV");
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$finish;
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end
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end
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endcase
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endgenerate
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endmodule
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module GP_COUNT8(
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input wire CLK,
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input wire RST,
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@ -41,6 +327,13 @@ module GP_COUNT8(
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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initial begin
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if(CLKIN_DIVIDE != 1) begin
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$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
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$finish;
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end
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end
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reg[7:0] count = COUNT_TO;
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//Combinatorially output underflow flag whenever we wrap low
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