mirror of https://github.com/YosysHQ/yosys.git
Improved ice40_ffinit error reporting
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7cddab0788
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@ -57,6 +57,7 @@ struct Ice40FfinitPass : public Pass {
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SigMap sigmap(module);
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pool<Wire*> init_wires;
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dict<SigBit, State> initbits;
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dict<SigBit, SigBit> initbit_to_wire;
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pool<SigBit> handled_initbits;
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for (auto wire : module->selected_wires())
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@ -78,11 +79,14 @@ struct Ice40FfinitPass : public Pass {
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if (initbits.count(bit)) {
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if (initbits.at(bit) != val)
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log_error("Conflicting init values for signal %s.\n", log_signal(bit));
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log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
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log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
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log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
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continue;
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}
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initbits[bit] = val;
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initbit_to_wire[bit] = SigBit(wire, i);
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}
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}
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