mirror of https://github.com/YosysHQ/yosys.git
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
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Clifford Wolf
parent
7ff802e199
commit
1277d1bcb8
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@ -243,13 +243,293 @@ module SB_DFFNES (output reg Q, input C, E, S, D);
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Q <= D;
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endmodule
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// Packed IceStorm Logic Cells
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// SiliconBlue RAM Cells
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module ICESTORM_CARRYCONST (output COUT);
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parameter [0:0] CARRYCONST = 0;
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assign COUT = CARRYCONST;
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module SB_RAM40_4K (
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output reg [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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// MODE 0: 256 x 16
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// MODE 1: 512 x 8
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// MODE 2: 1024 x 4
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// MODE 3: 2048 x 2
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parameter WRITE_MODE = 0;
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parameter READ_MODE = 0;
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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`ifndef BLACKBOX
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integer i;
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reg [15:0] memory [0:255];
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initial begin
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for (i=0; i<16; i=i+1) begin
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memory[ 0*16 + i] <= INIT_0[16*i +: 16];
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memory[ 1*16 + i] <= INIT_1[16*i +: 16];
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memory[ 2*16 + i] <= INIT_2[16*i +: 16];
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memory[ 3*16 + i] <= INIT_3[16*i +: 16];
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memory[ 4*16 + i] <= INIT_4[16*i +: 16];
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memory[ 5*16 + i] <= INIT_5[16*i +: 16];
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memory[ 6*16 + i] <= INIT_6[16*i +: 16];
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memory[ 7*16 + i] <= INIT_7[16*i +: 16];
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memory[ 8*16 + i] <= INIT_8[16*i +: 16];
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memory[ 9*16 + i] <= INIT_9[16*i +: 16];
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memory[10*16 + i] <= INIT_A[16*i +: 16];
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memory[11*16 + i] <= INIT_B[16*i +: 16];
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memory[12*16 + i] <= INIT_C[16*i +: 16];
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memory[13*16 + i] <= INIT_D[16*i +: 16];
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memory[14*16 + i] <= INIT_E[16*i +: 16];
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memory[15*16 + i] <= INIT_F[16*i +: 16];
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end
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end
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always @(posedge WCLK) begin
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if (WE && WCLKE) begin
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if (WRITE_MODE == 0) begin
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for (i=0; i<16; i=i+1)
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if (MASK[i]) memory[WADDR[7:0]][i] <= WDATA[i];
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end
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if (WRITE_MODE == 1) begin
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for (i=0; i<2; i=i+1)
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if (WADDR[0] == i) memory[WADDR[8:1]][i*8 +: 8] <= WDATA[i][7:0];
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end
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if (WRITE_MODE == 2) begin
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for (i=0; i<4; i=i+1)
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if (WADDR[1:0] == i) memory[WADDR[9:2]][i*4 +: 4] <= WDATA[i][3:0];
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end
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if (WRITE_MODE == 3) begin
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for (i=0; i<8; i=i+1)
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if (WADDR[2:0] == i) memory[WADDR[10:3]][i*2 +: 2] <= WDATA[i][1:0];
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end
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end
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end
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always @(posedge RCLK) begin
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if (RE && RCLKE) begin
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if (READ_MODE == 0) begin
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RDATA <= memory[RADDR[7:0]];
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end
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if (READ_MODE == 1) begin
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RDATA <= memory[RADDR[8:1]][RADDR[0]*8 +: 8];
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end
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if (READ_MODE == 2) begin
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RDATA <= memory[RADDR[9:2]][RADDR[1:0]*4 +: 4];
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end
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if (READ_MODE == 3) begin
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RDATA <= memory[RADDR[10:3]][RADDR[2:0]*2 +: 2];
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end
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end
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end
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`endif
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endmodule
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module SB_RAM40_4KNR (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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parameter WRITE_MODE = 0;
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parameter READ_MODE = 0;
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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.INIT_0 (INIT_0 ),
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.INIT_1 (INIT_1 ),
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.INIT_2 (INIT_2 ),
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.INIT_3 (INIT_3 ),
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.INIT_4 (INIT_4 ),
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.INIT_5 (INIT_5 ),
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.INIT_6 (INIT_6 ),
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.INIT_7 (INIT_7 ),
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.INIT_8 (INIT_8 ),
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.INIT_9 (INIT_9 ),
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.INIT_A (INIT_A ),
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.INIT_B (INIT_B ),
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLK),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (WCLK ),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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endmodule
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module SB_RAM40_4KNW (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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parameter WRITE_MODE = 0;
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parameter READ_MODE = 0;
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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.INIT_0 (INIT_0 ),
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.INIT_1 (INIT_1 ),
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.INIT_2 (INIT_2 ),
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.INIT_3 (INIT_3 ),
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.INIT_4 (INIT_4 ),
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.INIT_5 (INIT_5 ),
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.INIT_6 (INIT_6 ),
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.INIT_7 (INIT_7 ),
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.INIT_8 (INIT_8 ),
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.INIT_9 (INIT_9 ),
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.INIT_A (INIT_A ),
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.INIT_B (INIT_B ),
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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) RAM (
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.RDATA(RDATA),
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.RCLK (RCLK ),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (~WCLK),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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endmodule
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module SB_RAM40_4KNRNW (
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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input [10:0] WADDR,
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input [15:0] MASK, WDATA
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);
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parameter WRITE_MODE = 0;
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parameter READ_MODE = 0;
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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.INIT_0 (INIT_0 ),
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.INIT_1 (INIT_1 ),
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.INIT_2 (INIT_2 ),
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.INIT_3 (INIT_3 ),
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.INIT_4 (INIT_4 ),
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.INIT_5 (INIT_5 ),
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.INIT_6 (INIT_6 ),
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.INIT_7 (INIT_7 ),
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.INIT_8 (INIT_8 ),
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.INIT_9 (INIT_9 ),
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.INIT_A (INIT_A ),
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.INIT_B (INIT_B ),
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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) RAM (
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.RDATA(RDATA),
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.RCLK (~RCLK),
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.RCLKE(RCLKE),
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.RE (RE ),
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.RADDR(RADDR),
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.WCLK (~WCLK),
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.WCLKE(WCLKE),
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.WE (WE ),
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.WADDR(WADDR),
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.MASK (MASK ),
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.WDATA(WDATA)
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);
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endmodule
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// Packed IceStorm Logic Cells
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module ICESTORM_LC (
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input I0, I1, I2, I3, CIN, CLK, CEN, SR,
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output O, COUT
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@ -272,20 +552,16 @@ module ICESTORM_LC (
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wire polarized_clk;
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assign polarized_clk = CLK ^ NEG_CLK;
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wire filtered_cen, filtered_sr;
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assign filtered_cen = CEN === 1'bz ? 1'b1 : CEN;
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assign filtered_sr = SR === 1'bz ? 1'b0 : SR;
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reg o_reg;
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always @(posedge polarized_clk)
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if (filtered_cen)
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o_reg <= filtered_sr ? SET_NORESET : lut_o;
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if (CEN)
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o_reg <= SR ? SET_NORESET : lut_o;
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reg o_reg_async;
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always @(posedge polarized_clk, posedge filtered_sr)
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if (filtered_sr)
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always @(posedge polarized_clk, posedge SR)
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if (SR)
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o_reg <= SET_NORESET;
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else if (filtered_cen)
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else if (CEN)
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o_reg <= lut_o;
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assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
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