mirror of https://github.com/YosysHQ/yosys.git
Various small cleanups in stdcells.v techmap code
This commit is contained in:
Clifford Wolf
parent
15acf593e7
commit
b3b00f1bf4
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@ -115,7 +115,6 @@ endmodule
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module \$reduce_xor ;
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endmodule
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// --------------------------------------------------------
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(* techmap_simplemap *)
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@ -218,7 +217,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
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localparam WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -271,7 +270,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = Y_WIDTH;
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localparam WIDTH = Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -324,7 +323,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
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localparam WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -387,11 +386,11 @@ output X, Y;
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// {t1, t2} = A + B
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wire t1, t2, t3;
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\$_AND_ gate1 ( .A(A), .B(B), .Y(t1) );
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\$_XOR_ gate2 ( .A(A), .B(B), .Y(t2) );
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\$_AND_ gate3 ( .A(t2), .B(C), .Y(t3) );
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\$_XOR_ gate4 ( .A(t2), .B(C), .Y(Y) );
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\$_OR_ gate5 ( .A(t1), .B(t3), .Y(X) );
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\$_AND_ gate1 ( .A(A), .B(B), .Y(t1) );
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\$_XOR_ gate2 ( .A(A), .B(B), .Y(t2) );
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\$_AND_ gate3 ( .A(t2), .B(C), .Y(t3) );
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\$_XOR_ gate4 ( .A(t2), .B(C), .Y(Y) );
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\$_OR_ gate5 ( .A(t1), .B(t3), .Y(X) );
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endmodule
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@ -438,7 +437,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -446,8 +445,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(WIDTH)
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@ -487,7 +486,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -495,8 +494,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(WIDTH)
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@ -536,7 +535,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -544,8 +543,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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assign Y = ~|(A_buf ^ B_buf);
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@ -561,7 +560,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -569,8 +568,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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assign Y = |(A_buf ^ B_buf);
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@ -586,7 +585,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -594,8 +593,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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assign Y = ~|(A_buf ^ B_buf);
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@ -611,7 +610,7 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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@ -619,8 +618,8 @@ output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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assign Y = |(A_buf ^ B_buf);
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@ -697,8 +696,8 @@ input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(Y_WIDTH)
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@ -726,8 +725,8 @@ input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(Y_WIDTH)
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@ -775,8 +774,8 @@ input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__arraymul #(
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.WIDTH(Y_WIDTH)
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@ -837,12 +836,12 @@ input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y, R;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
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assign A_buf_u = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
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assign B_buf_u = A_SIGNED && B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
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assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
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assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
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\$__div_mod_u #(
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.WIDTH(WIDTH)
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@ -872,9 +871,6 @@ input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] Y_buf;
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wire [Y_WIDTH-1:0] Y_div_zero;
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\$__div_mod #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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@ -884,20 +880,9 @@ wire [Y_WIDTH-1:0] Y_div_zero;
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) div_mod (
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.A(A),
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.B(B),
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.Y(Y_buf)
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.Y(Y)
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);
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// explicitly force the division-by-zero behavior found in other synthesis tools
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generate begin
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if (A_SIGNED && B_SIGNED) begin:make_div_zero
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assign Y_div_zero = A[A_WIDTH-1] ? {Y_WIDTH{1'b0}} | 1'b1 : {Y_WIDTH{1'b1}};
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end else begin:make_div_zero
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assign Y_div_zero = {A_WIDTH{1'b1}};
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end
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end endgenerate
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assign Y = B ? Y_buf : Y_div_zero;
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endmodule
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// --------------------------------------------------------
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@ -914,9 +899,6 @@ input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] Y_buf;
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wire [Y_WIDTH-1:0] Y_div_zero;
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\$__div_mod #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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@ -926,21 +908,9 @@ wire [Y_WIDTH-1:0] Y_div_zero;
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) div_mod (
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.A(A),
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.B(B),
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.R(Y_buf)
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.R(Y)
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);
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// explicitly force the division-by-zero behavior found in other synthesis tools
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localparam div_zero_copy_a_bits = A_WIDTH < B_WIDTH ? A_WIDTH : B_WIDTH;
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generate begin
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if (A_SIGNED && B_SIGNED) begin:make_div_zero
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assign Y_div_zero = $signed(A[div_zero_copy_a_bits-1:0]);
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end else begin:make_div_zero
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assign Y_div_zero = $unsigned(A[div_zero_copy_a_bits-1:0]);
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end
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end endgenerate
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assign Y = B ? Y_buf : Y_div_zero;
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endmodule
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/****
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