mirror of https://github.com/YosysHQ/yosys.git
Using maccmap for $macc and $mul techmap
This commit is contained in:
Clifford Wolf
parent
c50b841b29
commit
dd887cc025
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@ -455,102 +455,8 @@ endmodule
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// Multiply
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// --------------------------------------------------------
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module \$__acc_set (acc_new, value);
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parameter WIDTH = 1;
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output reg [2*WIDTH-1:0] acc_new;
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input [WIDTH-1:0] value;
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wire [1023:0] _TECHMAP_DO_ = "proc;;;";
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integer k;
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always @* begin
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for (k = 0; k < WIDTH; k = k+1) begin
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acc_new[2*k +: 2] = value[k];
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end
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end
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endmodule
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module \$__acc_add (acc_new, acc_old, value);
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parameter WIDTH = 1;
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output reg [2*WIDTH-1:0] acc_new;
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input [2*WIDTH-1:0] acc_old;
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input [WIDTH-1:0] value;
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wire [1023:0] _TECHMAP_DO_ = "proc; simplemap; opt -purge";
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integer k;
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reg a, b, c;
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always @* begin
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for (k = 0; k < WIDTH; k = k+1) begin
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a = acc_old[2*k];
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b = k ? acc_old[2*k-1] : 1'b0;
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c = value[k];
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acc_new[2*k] = (a ^ b) ^ c;
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acc_new[2*k+1] = (a & b) | ((a ^ b) & c);
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end
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end
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endmodule
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module \$__acc_get (value, acc);
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parameter WIDTH = 1;
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output reg [WIDTH-1:0] value;
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input [2*WIDTH-1:0] acc;
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wire [1023:0] _TECHMAP_DO_ = "proc;;;";
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integer k;
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always @* begin
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// at the end of the multiplier chain the carry-save accumulator
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// should also have propagated all carries. thus we just need to
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// copy the even bits from the carry accumulator to the output.
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for (k = 0; k < WIDTH; k = k+1) begin
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value[k] = acc[2*k];
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end
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end
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endmodule
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module \$__acc_mul (A, B, Y);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc;;";
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integer i;
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reg [WIDTH-1:0] x;
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reg [2*WIDTH-1:0] y;
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(* via_celltype = "\\$__acc_set acc_new" *)
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(* via_celltype_defparam_WIDTH = WIDTH *)
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function [2*WIDTH-1:0] acc_set;
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input [WIDTH-1:0] value;
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endfunction
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(* via_celltype = "\\$__acc_add acc_new" *)
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(* via_celltype_defparam_WIDTH = WIDTH *)
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function [2*WIDTH-1:0] acc_add;
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input [2*WIDTH-1:0] acc_old;
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input [WIDTH-1:0] value;
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endfunction
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(* via_celltype = "\\$__acc_get value" *)
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(* via_celltype_defparam_WIDTH = WIDTH *)
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function [WIDTH-1:0] acc_get;
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input [2*WIDTH-1:0] acc;
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endfunction
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always @* begin
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x = B;
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y = acc_set(A[0] ? x : 1'b0);
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for (i = 1; i < WIDTH; i = i+1) begin
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x = {x[WIDTH-2:0], 1'b0};
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y = acc_add(y, A[i] ? x : 1'b0);
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end
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end
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assign Y = acc_get(y);
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(* techmap_maccmap *)
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module \$macc ;
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endmodule
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module \$mul (A, B, Y);
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@ -566,105 +472,25 @@ module \$mul (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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localparam [ 3:0] CONFIG_WIDTH_BITS = 15;
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localparam [ 0:0] CONFIG_IS_SIGNED = A_SIGNED && B_SIGNED;
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localparam [ 0:0] CONFIG_DO_SUBTRACT = 0;
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localparam [14:0] CONFIG_A_WIDTH = A_WIDTH;
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localparam [14:0] CONFIG_B_WIDTH = B_WIDTH;
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\$__acc_mul #(
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.WIDTH(Y_WIDTH)
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\$macc #(
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.CONFIG({CONFIG_B_WIDTH, CONFIG_A_WIDTH, CONFIG_DO_SUBTRACT, CONFIG_IS_SIGNED, CONFIG_WIDTH_BITS}),
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.CONFIG_WIDTH(15 + 15 + 2 + 4),
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.A_WIDTH(B_WIDTH + A_WIDTH),
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.B_WIDTH(0),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_buf),
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.B(B_buf),
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.A({B, A}),
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.B(),
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.Y(Y)
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);
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endmodule
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module \$macc (A, B, Y);
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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parameter CONFIG = 4'b0000;
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parameter CONFIG_WIDTH = 4;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output reg [Y_WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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localparam integer num_bits = CONFIG[3:0];
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localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
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localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
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function [2*num_ports*num_abits-1:0] get_port_offsets;
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input [CONFIG_WIDTH-1:0] cfg;
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integer i, cursor;
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begin
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cursor = 0;
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get_port_offsets = 0;
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for (i = 0; i < num_ports; i = i+1) begin
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get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
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cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
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get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
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cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
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end
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end
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endfunction
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localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
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`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])
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`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
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`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
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`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
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`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])
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`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
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integer i, j;
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reg [Y_WIDTH-1:0] tmp_a, tmp_b;
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always @* begin
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Y = 0;
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for (i = 0; i < num_ports; i = i+1)
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begin
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tmp_a = 0;
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tmp_b = 0;
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for (j = 0; j < `PORT_SIZE_A; j = j+1)
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tmp_a[j] = A[`PORT_OFFSET_A + j];
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if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
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for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
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tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
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for (j = 0; j < `PORT_SIZE_B; j = j+1)
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tmp_b[j] = A[`PORT_OFFSET_B + j];
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if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
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for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
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tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
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if (`PORT_SIZE_B > 0)
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tmp_a = tmp_a * tmp_b;
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if (`PORT_DO_SUBTRACT)
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Y = Y - tmp_a;
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else
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Y = Y + tmp_a;
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end
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for (i = 0; i < B_WIDTH; i = i+1) begin
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Y = Y + B[i];
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end
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end
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`undef PORT_IS_SIGNED
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`undef PORT_DO_SUBTRACT
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`undef PORT_SIZE_A
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`undef PORT_SIZE_B
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`undef PORT_OFFSET_A
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`undef PORT_OFFSET_B
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endmodule
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// --------------------------------------------------------
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// Divide and Modulo
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