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Fixed "test_cell -simlib all"

This commit is contained in:
Clifford Wolf 2014-09-01 15:37:56 +02:00
parent c7f81e4e49
commit 9923762461
1 changed files with 3 additions and 2 deletions
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5
techlibs/common/simlib.v
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@ -108,12 +108,13 @@ parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] tmp;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = -$signed(A);
assign tmp = $signed(A), Y = -tmp;
end else begin:BLOCK2
assign Y = -A;
assign tmp = A, Y = -tmp;
end
endgenerate