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Fixed simlib entries for $memrd and $memwr

This commit is contained in:
Clifford Wolf 2014-12-30 13:33:29 +01:00
parent 120a8313d9
commit ba43cf5807
1 changed files with 2 additions and 0 deletions
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2
techlibs/common/simlib.v
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@ -1449,6 +1449,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter TRANSPARENT = 0;
input CLK;
input [ABITS-1:0] ADDR;
@ -1473,6 +1474,7 @@ parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter PRIORITY = 0;
input CLK;
input [WIDTH-1:0] EN;