mirror of https://github.com/YosysHQ/yosys.git
Added simulation timescale declaration
This commit is contained in:
parent
f103bfb9ba
commit
a0c19aae55
|
@ -1,3 +1,5 @@
|
|||
`timescale 1ns/1ps;
|
||||
|
||||
module GP_2LUT(input IN0, IN1, output OUT);
|
||||
parameter [3:0] INIT = 0;
|
||||
assign OUT = INIT[{IN1, IN0}];
|
||||
|
|
Loading…
Reference in New Issue