mirror of https://github.com/YosysHQ/yosys.git
improved iCE40 SB_RAM40_4K simulation model
This commit is contained in:
Clifford Wolf
parent
bd0597137d
commit
4cc4400514
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@ -278,23 +278,80 @@ module SB_RAM40_4K (
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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`ifndef BLACKBOX
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wire [15:0] WMASK_I;
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wire [15:0] RMASK_I;
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reg [15:0] RDATA_I;
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wire [15:0] WDATA_I;
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generate
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case (WRITE_MODE)
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0: assign WDATA_I = WDATA;
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1: assign WDATA_I = {WDATA[14], WDATA[12], WDATA[10], WDATA[ 8],
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WDATA[ 6], WDATA[ 4], WDATA[ 2], WDATA[ 0]};
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2: assign WDATA_I = {WDATA[13], WDATA[9], WDATA[5], WDATA[1]};
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3: assign WDATA_I = {WDATA[11], WDATA[3]};
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0: assign WMASK_I = MASK;
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1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
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WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
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2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
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WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
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WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
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WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
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3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
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WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
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WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
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WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
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WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
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WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
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WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
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WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
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endcase
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case (READ_MODE)
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0: assign RMASK_I = 16'b 0000_0000_0000_0000;
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1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
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RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
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2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
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RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
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RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
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RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
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3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
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RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
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RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
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RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
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RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
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RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
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RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
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RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
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endcase
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case (WRITE_MODE)
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0: assign WDATA_I = WDATA;
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1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
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WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
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WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
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WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
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2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
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WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
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WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
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WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
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3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
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WDATA[11], WDATA[11], WDATA[11], WDATA[11],
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WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
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WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
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endcase
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case (READ_MODE)
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0: assign RDATA = RDATA_I;
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1: assign RDATA = {1'b0, RDATA_I[7], 1'b0, RDATA_I[6], 1'b0, RDATA_I[5], 1'b0, RDATA_I[4],
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1'b0, RDATA_I[3], 1'b0, RDATA_I[2], 1'b0, RDATA_I[1], 1'b0, RDATA_I[0]};
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2: assign RDATA = {2'b00, RDATA_I[3], 3'b000, RDATA_I[2], 3'b000, RDATA_I[1], 3'b000, RDATA_I[0], 1'b0};
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3: assign RDATA = {4'b0000, RDATA_I[1], 7'b0000000, RDATA_I[0], 3'b000};
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1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
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1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
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2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
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3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
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endcase
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endgenerate
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@ -324,62 +381,29 @@ module SB_RAM40_4K (
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always @(posedge WCLK) begin
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if (WE && WCLKE) begin
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if (WRITE_MODE == 0) begin
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if (!MASK[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
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if (!MASK[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
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if (!MASK[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
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if (!MASK[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
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if (!MASK[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
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if (!MASK[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
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if (!MASK[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
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if (!MASK[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
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if (!MASK[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
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if (!MASK[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
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if (!MASK[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
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if (!MASK[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
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if (!MASK[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
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if (!MASK[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
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if (!MASK[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
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if (!MASK[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
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if (!MASK[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
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end
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if (WRITE_MODE == 1) begin
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if (WADDR[0] == 0) memory[WADDR[8:1]][0*8 +: 8] <= WDATA_I[7:0];
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if (WADDR[0] == 1) memory[WADDR[8:1]][1*8 +: 8] <= WDATA_I[7:0];
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end
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if (WRITE_MODE == 2) begin
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if (WADDR[1:0] == 0) memory[WADDR[9:2]][0*4 +: 4] <= WDATA_I[3:0];
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if (WADDR[1:0] == 1) memory[WADDR[9:2]][1*4 +: 4] <= WDATA_I[3:0];
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if (WADDR[1:0] == 2) memory[WADDR[9:2]][2*4 +: 4] <= WDATA_I[3:0];
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if (WADDR[1:0] == 3) memory[WADDR[9:2]][3*4 +: 4] <= WDATA_I[3:0];
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end
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if (WRITE_MODE == 3) begin
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if (WADDR[2:0] == 0) memory[WADDR[10:3]][0*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 1) memory[WADDR[10:3]][1*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 2) memory[WADDR[10:3]][2*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 3) memory[WADDR[10:3]][3*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 4) memory[WADDR[10:3]][4*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 5) memory[WADDR[10:3]][5*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 6) memory[WADDR[10:3]][6*2 +: 2] <= WDATA_I[1:0];
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if (WADDR[2:0] == 7) memory[WADDR[10:3]][7*2 +: 2] <= WDATA_I[1:0];
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end
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if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
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if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
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if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
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if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
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if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
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if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
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if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
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if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
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if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
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if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
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if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
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if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
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if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
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if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
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if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
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if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
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if (!WMASK_I[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
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end
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end
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always @(posedge RCLK) begin
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if (RE && RCLKE) begin
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if (READ_MODE == 0) begin
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RDATA_I <= memory[RADDR[7:0]];
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end
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if (READ_MODE == 1) begin
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RDATA_I <= memory[RADDR[8:1]][RADDR[0]*8 +: 8];
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end
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if (READ_MODE == 2) begin
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RDATA_I <= memory[RADDR[9:2]][RADDR[1:0]*4 +: 4];
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end
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if (READ_MODE == 3) begin
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RDATA_I <= memory[RADDR[10:3]][RADDR[2:0]*2 +: 2];
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end
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RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
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end
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end
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`endif
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