Fixed typo in port name

2016-05-07 21:14:42 -07:00 · 2016-05-07 21:14:42 -07:00 · 41bbad4e4c
parent b5171541cd
commit 41bbad4e4c
1 changed files with 1 additions and 1 deletions
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 	
 	reg[15:0] shreg = 0;
 	
-	always @(posedge clk, negedge nRST) begin
+	always @(posedge CLK, negedge nRST) begin
 		
 		if(!nRST)
 			shreg = 0;