mirror of https://github.com/YosysHQ/yosys.git
326 lines
6.3 KiB
Verilog
326 lines
6.3 KiB
Verilog
`timescale 1ns/1ps
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_ABUF(input wire IN, output wire OUT);
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assign OUT = IN;
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//cannot simulate mixed signal IP
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endmodule
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module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
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parameter BANDWIDTH = "HIGH";
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parameter VIN_ATTEN = 1;
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parameter VIN_ISRC_EN = 0;
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parameter HYSTERESIS = 0;
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initial OUT = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_BANDGAP(output reg OK, output reg VOUT);
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parameter AUTO_PWRDN = 1;
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parameter CHOPPER_EN = 1;
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parameter OUT_DELAY = 100;
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//cannot simulate mixed signal IP
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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reg[7:0] count = COUNT_TO;
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//Combinatorially output whenever we wrap low
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always @(*) begin
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OUT <= (count == 8'h0);
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
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//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
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always @(posedge CLK) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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/*
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if((RESET_MODE == "RISING") && RST)
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count <= 0;
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if((RESET_MODE == "FALLING") && !RST)
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count <= 0;
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if((RESET_MODE == "BOTH") && RST)
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count <= 0;
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*/
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end
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_IBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_IOBUF(input IN, input OE, output OUT, inout IO);
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assign OUT = IO;
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assign IO = OE ? IN : 1'bz;
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endmodule
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module GP_INV(input IN, output OUT);
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assign OUT = ~IN;
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endmodule
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module GP_LFOSC(input PWRDN, output reg CLKOUT);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter OUT_DIV = 1;
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initial CLKOUT = 0;
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//auto powerdown not implemented for simulation
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//output dividers not implemented for simulation
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always begin
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if(PWRDN)
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CLKOUT = 0;
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else begin
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//half period of 1730 Hz
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#289017;
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CLKOUT = ~CLKOUT;
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end
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end
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endmodule
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module GP_OBUF(input IN, output OUT);
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assign OUT = IN;
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endmodule
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module GP_OBUFT(input IN, input OE, output OUT);
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assign OUT = OE ? IN : 1'bz;
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endmodule
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module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
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parameter GAIN = 1;
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parameter INPUT_MODE = "SINGLE";
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initial VOUT = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_POR(output reg RST_DONE);
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parameter POR_TIME = 500;
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initial begin
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RST_DONE = 0;
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if(POR_TIME == 4)
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#4000;
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else if(POR_TIME == 500)
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#500000;
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else begin
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$display("ERROR: bad POR_TIME for GP_POR cell");
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$finish;
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end
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RST_DONE = 1;
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end
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endmodule
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module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter PRE_DIV = 1;
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parameter FABRIC_DIV = 1;
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parameter OSC_FREQ = "25k";
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initial CLKOUT_PREDIV = 0;
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initial CLKOUT_FABRIC = 0;
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//output dividers not implemented for simulation
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//auto powerdown not implemented for simulation
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always begin
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if(PWRDN) begin
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CLKOUT_PREDIV = 0;
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CLKOUT_FABRIC = 0;
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end
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else begin
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if(OSC_FREQ == "25k") begin
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//half period of 25 kHz
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#20000;
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end
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else begin
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//half period of 2 MHz
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#250;
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end
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CLKOUT_PREDIV = ~CLKOUT_PREDIV;
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CLKOUT_FABRIC = ~CLKOUT_FABRIC;
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end
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end
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endmodule
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module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter PRE_DIV = 1;
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parameter FABRIC_DIV = 1;
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initial CLKOUT_PREDIV = 0;
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initial CLKOUT_FABRIC = 0;
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//output dividers not implemented for simulation
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//auto powerdown not implemented for simulation
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always begin
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if(PWRDN) begin
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CLKOUT_PREDIV = 0;
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CLKOUT_FABRIC = 0;
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end
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else begin
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//half period of 27 MHz
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#18.518;
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CLKOUT_PREDIV = ~CLKOUT_PREDIV;
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CLKOUT_FABRIC = ~CLKOUT_FABRIC;
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end
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end
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endmodule
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module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
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parameter OUTA_TAP = 1;
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parameter OUTA_INVERT = 0;
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parameter OUTB_TAP = 1;
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reg[15:0] shreg = 0;
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always @(posedge CLK, negedge nRST) begin
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if(!nRST)
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shreg = 0;
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else
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shreg <= {shreg[14:0], IN};
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end
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assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
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assign OUTB = shreg[OUTB_TAP - 1];
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endmodule
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//keep constraint needed to prevent optimization since we have no outputs
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(* keep *)
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module GP_SYSRESET(input RST);
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parameter RESET_MODE = "RISING";
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//cannot simulate whole system reset
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endmodule
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module GP_VDD(output OUT);
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assign OUT = 1;
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endmodule
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module GP_VREF(input VIN, output reg VOUT);
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parameter VIN_DIV = 1;
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parameter VREF = 0;
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//cannot simulate mixed signal IP
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endmodule
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module GP_VSS(output OUT);
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assign OUT = 0;
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endmodule
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