mirror of https://github.com/YosysHQ/yosys.git
Fixed techmap of $reduce_xnor with multi-bit outputs
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@ -351,9 +351,15 @@ endgenerate
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assign buffer[0] = A[0];
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\$_INV_ gate_inv (
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.A(buffer[A_WIDTH-1]),
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.Y(Y)
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.Y(Y[0])
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);
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generate
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if (Y_WIDTH > 1) begin:V
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assign Y[Y_WIDTH-1:1] = 0;
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end
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endgenerate
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endmodule
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// --------------------------------------------------------
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