riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

greenpak4: Added INT pin to GP_SPI

This commit is contained in:
Andrew Zonenberg 2016-12-21 11:35:29 +08:00
parent 6b526e9382
commit ada98844b9
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/greenpak4/cells_sim.v
View File

@ -596,10 +596,12 @@ module GP_SPI(
input[7:0] TXD_HIGH,
input[7:0] TXD_LOW,
output reg[7:0] RXD_HIGH,
output reg[7:0] RXD_LOW);
output reg[7:0] RXD_LOW,
output reg INT);
initial DOUT_HIGH = 0;
initial DOUT_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width
parameter SPI_CPHA = 0; //SPI clock phase