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Xilinx mojo_counter example is now working

This commit is contained in:
Clifford Wolf 2013-10-27 08:21:56 +01:00
parent d9fa1e5a1d
commit 02f321b6fc
3 changed files with 9 additions and 4 deletions
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6
techlibs/xilinx/example_mojo_counter/example.sh
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@ -19,8 +19,12 @@ abc -lut 6; opt
# map internal cells to FPGA cells
techmap -map ../cells.v; opt
# insert clock buffers
select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d
iopadmap -inpad BUFGP O:I @clocks
# insert i/o buffers
iopadmap -outpad OBUF I:O -inpad BUFGP O:I
iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n
# write netlist
write_edif synth.edif

1
techlibs/xilinx/example_mojo_counter/example.ucf
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@ -2,6 +2,7 @@ NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
NET "clk" LOC = P56;
NET "ctrl" LOC = P1;
NET "led_0" LOC = P134;
NET "led_1" LOC = P133;

6
techlibs/xilinx/example_mojo_counter/example.v
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@ -1,13 +1,13 @@
module top(clk, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input clk;
input clk, ctrl;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
reg [31:0] counter;
always @(posedge clk)
counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
counter <= counter + (ctrl ? 4 : 1);
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;