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Removed old XST-based xilinx examples

This commit is contained in:
Clifford Wolf 2015-02-01 17:10:46 +01:00
parent 816fe6bbe0
commit 3cbfa3815e
11 changed files with 0 additions and 208 deletions
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10
techlibs/xilinx/example_mojo_counter/README
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This is a simple example for Yosys synthesis targeting the Mojo FPGA
development board [1, 2]. Simple script for xst-based synthesis (incl.
generation of reference edif files) and uploading to the board can be
found here [3].
[1] http://embeddedmicro.com/tutorials/mojo
[2] https://www.sparkfun.com/products/11953
[3] http://svn.clifford.at/handicraft/2013/mojo/

18
techlibs/xilinx/example_mojo_counter/example.sh
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#!/bin/bash
set -ex
XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
XILINX_PART=xc6slx9-2-tqg144
../../../yosys - <<- EOT
read_verilog example.v
synth_xilinx -edif synth.edif
EOT
$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf

14
techlibs/xilinx/example_mojo_counter/example.ucf
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NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
NET "clk" LOC = P56;
NET "ctrl" LOC = P1;
NET "led_0" LOC = P134;
NET "led_1" LOC = P133;
NET "led_2" LOC = P132;
NET "led_3" LOC = P131;
NET "led_4" LOC = P127;
NET "led_5" LOC = P126;
NET "led_6" LOC = P124;
NET "led_7" LOC = P123;

14
techlibs/xilinx/example_mojo_counter/example.v
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module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input clk, ctrl;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
reg [31:0] counter;
always @(posedge clk)
counter <= counter + (ctrl ? 4 : 1);
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
endmodule

12
techlibs/xilinx/example_sim_counter/counter.v
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module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule

61
techlibs/xilinx/example_sim_counter/counter_tb.v
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`timescale 1 ns / 1 ps
module testbench;
reg clk, en, rst;
wire [3:0] count;
counter uut_counter(
.clk(clk),
.count(count),
.en(en),
.rst(rst)
);
initial begin
clk <= 0;
forever begin
#50;
clk <= ~clk;
end
end
initial begin
@(posedge clk);
forever begin
@(posedge clk);
$display("%d", count);
end
end
initial begin
rst <= 1; en <= 0; @(posedge clk);
rst <= 1; en <= 0; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 1; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 1; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
rst <= 0; en <= 1; @(posedge clk);
rst <= 0; en <= 0; @(posedge clk);
$finish;
end
endmodule

23
techlibs/xilinx/example_sim_counter/run_sim.sh
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#!/bin/bash
set -ex
XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v
iverilog -o testbench_gold counter_tb.v counter.v
iverilog -o testbench_gate counter_tb.v testbench_synth.v \
$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
./testbench_gold > testbench_gold.txt
./testbench_gate > testbench_gate.txt
if diff -u testbench_gold.txt testbench_gate.txt; then
set +x; echo; echo; banner " PASS "
else
exit 1
fi
rm -f testbench_{synth,gold,gate,mapped}*

10
techlibs/xilinx/example_zed_counter/README
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This is a simple example for Yosys synthesis targeting the ZED FPGA
development board [1, 2]. Simple script for xst-based synthesis (incl.
generation of reference edif files) and uploading to the board can be
found here [3].
[1] http://www.zedboard.org/
[2] https://www.xilinx.com/zynq/
[3] http://verilog.james.walms.co.uk/

18
techlibs/xilinx/example_zed_counter/example.sh
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#!/bin/bash
set -ex
XILINX_DIR=/opt/Xilinx/14.7/ISE_DS/ISE
XILINX_PART=xc7z020clg484-1
yosys - <<- EOT
read_verilog example.v
synth_xilinx -edif synth.edif
EOT
$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf
$XILINX_DIR/bin/lin64/promgen -w -b -p bin -o example.bin -u 0 example.bit -data_width 32

14
techlibs/xilinx/example_zed_counter/example.ucf
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NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
NET "clk" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET "ctrl" LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC"
NET "led_0" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_1" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_2" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_3" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_4" LOC = V22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_5" LOC = W22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_6" LOC = U19 | IOSTANDARD=LVCMOS33; # "LD0"
NET "led_7" LOC = U14 | IOSTANDARD=LVCMOS33; # "LD0"

14
techlibs/xilinx/example_zed_counter/example.v
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module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input clk, ctrl;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
reg [31:0] counter;
always @(posedge clk)
counter <= counter + (ctrl ? 4 : 1);
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
endmodule