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Added Xilinx MUXF7 and MUXF8 support

This commit is contained in:
Clifford Wolf 2015-01-15 13:50:04 +01:00
parent 2e36faeced
commit b197279f3c
2 changed files with 30 additions and 2 deletions
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28
techlibs/xilinx/cells.v
View File

@ -45,6 +45,34 @@ module \$lut (A, Y);
LUT6 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 7) begin:lut7
wire T0, T1;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
end else
if (WIDTH == 8) begin:lut8
wire T0, T1, T2, T3, T4, T5;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
end else begin:error
wire _TECHMAP_FAIL_ = 1;
end

4
techlibs/xilinx/synth_xilinx.cc
View File

@ -75,7 +75,7 @@ struct SynthXilinxPass : public Pass {
log(" synth -run fine\n");
log("\n");
log(" map_luts:\n");
log(" abc -lut 6\n");
log(" abc -lut 6:8\n");
log(" clean\n");
log("\n");
log(" map_cells:\n");
@ -147,7 +147,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "abc -lut 6");
Pass::call(design, "abc -lut 6:8");
Pass::call(design, "clean");
}