mirror of https://github.com/YosysHQ/yosys.git
Towards Xilinx bram support
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Clifford Wolf
parent
7cc5192125
commit
ec2eef89fa
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@ -12,7 +12,7 @@ bram $__XILINX_RAMB36_SDP72
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endbram
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bram $__XILINX_RAMB18_SDP36
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abits 10
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abits 9
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dbits 36
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groups 2
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ports 1 1
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@ -24,7 +24,7 @@ bram $__XILINX_RAMB18_SDP36
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endbram
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bram $__XILINX_RAMB18_TDP18
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abits 11
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abits 10
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dbits 18
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groups 2
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ports 1 1
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@ -36,7 +36,7 @@ bram $__XILINX_RAMB18_TDP18
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endbram
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bram $__XILINX_RAMB18_TDP9
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abits 12
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abits 11
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dbits 9
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groups 2
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ports 1 1
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@ -48,7 +48,7 @@ bram $__XILINX_RAMB18_TDP9
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endbram
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bram $__XILINX_RAMB18_TDP4
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abits 13
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abits 12
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dbits 4
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groups 2
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ports 1 1
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@ -60,7 +60,7 @@ bram $__XILINX_RAMB18_TDP4
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endbram
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bram $__XILINX_RAMB18_TDP2
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abits 14
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abits 13
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dbits 2
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groups 2
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ports 1 1
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@ -72,7 +72,7 @@ bram $__XILINX_RAMB18_TDP2
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endbram
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bram $__XILINX_RAMB18_TDP1
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abits 15
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abits 14
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dbits 1
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groups 2
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ports 1 1
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@ -94,14 +94,16 @@ match $__XILINX_RAMB18_SDP36
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min bits 4096
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min efficiency 5
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shuffle_enable 4
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# or_next_if_better
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or_next_if_better
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endmatch
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# match $__XILINX_RAMB18_TDP18
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# shuffle_enable 2
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# or_next_if_better
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# endmatch
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#
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match $__XILINX_RAMB18_TDP18
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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# or_next_if_better
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endmatch
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# match $__XILINX_RAMB18_TDP9
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# or_next_if_better
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# endmatch
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@ -167,10 +167,10 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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input [9:0] A1ADDR;
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output [17:0] A1DATA;
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input [8:0] B1ADDR;
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input [9:0] B1ADDR;
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input [17:0] B1DATA;
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input [1:0] B1EN;
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@ -21,6 +21,21 @@ module bram1_tb #(
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.RD_DATA(RD_DATA)
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);
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [ABITS-1:0] randaddr1;
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reg [ABITS-1:0] randaddr2;
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reg [ABITS-1:0] randaddr3;
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function [31:0] getaddr(input [3:0] n);
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begin
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case (n)
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@ -31,14 +46,19 @@ module bram1_tb #(
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4: getaddr = 'b11011 << (ABITS / 4);
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5: getaddr = 'b11011 << (2*ABITS / 4);
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6: getaddr = 'b11011 << (3*ABITS / 4);
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7: getaddr = 123456789;
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default: getaddr = 1 << (2*n-16);
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7: getaddr = randaddr1;
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8: getaddr = randaddr2;
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9: getaddr = randaddr3;
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default: begin
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getaddr = 1 << (2*n-16);
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if (!getaddr) getaddr = xorshift64_state;
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end
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endcase
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end
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endfunction
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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reg [DBITS-1:0] expected_rd;
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reg [DBITS-1:0] expected_rd, expected_rd_masked;
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event error;
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reg error_ind = 0;
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@ -47,12 +67,33 @@ module bram1_tb #(
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, bram1_tb);
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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randaddr1 = xorshift64_state;
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xorshift64_next;
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randaddr2 = xorshift64_state;
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xorshift64_next;
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randaddr3 = xorshift64_state;
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xorshift64_next;
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clk <= 0;
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for (i = 0; i < 256; i = i+1) begin
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WR_DATA <= i;
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if (DBITS > 64)
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WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
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else
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WR_DATA <= xorshift64_state;
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xorshift64_next;
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WR_ADDR <= getaddr(i[7:4]);
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xorshift64_next;
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RD_ADDR <= getaddr(i[3:0]);
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WR_EN <= ^i;
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xorshift64_next;
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#1; clk <= 1;
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#1; clk <= 0;
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@ -65,13 +106,11 @@ module bram1_tb #(
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if (WR_EN) memory[WR_ADDR] = WR_DATA;
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end
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for (j = 0; j < DBITS; j = j+1) begin
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if (expected_rd[j] === 1'bx)
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expected_rd[j] = RD_DATA[j];
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end
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for (j = 0; j < DBITS; j = j+1)
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expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
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$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
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if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
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$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
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if (expected_rd_masked !== RD_DATA) begin -> error; error_ind = ~error_ind; end
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end
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end
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endmodule
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