mirror of https://github.com/YosysHQ/yosys.git
122 lines
1.6 KiB
Plaintext
122 lines
1.6 KiB
Plaintext
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bram $__XILINX_RAMB36_SDP72
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abits 9
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dbits 72
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 8
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_SDP36
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abits 9
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dbits 36
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 4
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP18
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abits 10
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dbits 18
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 2
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP9
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abits 11
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dbits 9
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP4
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abits 12
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dbits 4
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP2
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abits 13
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dbits 2
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB18_TDP1
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abits 14
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 2 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__XILINX_RAMB36_SDP72
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min bits 4096
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min efficiency 5
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shuffle_enable 8
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP36
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min bits 4096
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min efficiency 5
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shuffle_enable 4
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_TDP18
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min bits 4096
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min efficiency 5
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shuffle_enable 2
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# or_next_if_better
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endmatch
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# match $__XILINX_RAMB18_TDP9
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB18_TDP4
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB18_TDP2
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB18_TDP1
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# endmatch
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