mirror of https://github.com/YosysHQ/yosys.git
Clifford Wolf
GitHub
commit
6afee022ad
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@ -0,0 +1,7 @@
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OBJS += techlibs/coolrunner2/synth_coolrunner2.o
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OBJS += techlibs/coolrunner2/coolrunner2_sop.o
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))
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@ -0,0 +1,19 @@
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module $_DLATCH_P_(input E, input D, output Q);
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LDCP _TECHMAP_REPLACE_ (
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.D(D),
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.G(E),
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.Q(Q),
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.PRE(1'b0),
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.CLR(1'b0)
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);
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endmodule
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module $_DLATCH_N_(input E, input D, output Q);
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LDCP_N _TECHMAP_REPLACE_ (
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.D(D),
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.G(E),
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.Q(Q),
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.PRE(1'b0),
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.CLR(1'b0)
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);
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endmodule
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@ -0,0 +1,246 @@
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module IBUF(input I, output O);
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assign O = I;
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endmodule
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module IOBUFE(input I, input E, output O, inout IO);
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assign O = IO;
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assign IO = E ? I : 1'bz;
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endmodule
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module ANDTERM(IN, IN_B, OUT);
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parameter TRUE_INP = 0;
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parameter COMP_INP = 0;
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input [TRUE_INP-1:0] IN;
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input [COMP_INP-1:0] IN_B;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 1;
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for (i = 0; i < TRUE_INP; i=i+1)
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OUT = OUT & IN[i];
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for (i = 0; i < COMP_INP; i=i+1)
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OUT = OUT & ~IN_B[i];
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end
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endmodule
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module ORTERM(IN, OUT);
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parameter WIDTH = 0;
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input [WIDTH-1:0] IN;
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output reg OUT;
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integer i;
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always @(*) begin
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OUT = 0;
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for (i = 0; i < WIDTH; i=i+1) begin
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OUT = OUT | IN[i];
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end
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end
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endmodule
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module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
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parameter INVERT_OUT = 0;
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input IN_PTC;
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input IN_ORTERM;
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output wire OUT;
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wire xor_intermed;
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assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
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assign xor_intermed = IN_ORTERM ^ IN_PTC;
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endmodule
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module FDCP (C, PRE, CLR, D, Q);
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parameter INIT = 0;
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input C, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @(posedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q <= 0;
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else if (PRE == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module FDCP_N (C, PRE, CLR, D, Q);
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parameter INIT = 0;
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input C, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @(negedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q <= 0;
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else if (PRE == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module LDCP (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 1)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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module LDCP_N (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 0)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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module BUFG(I, O);
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input I;
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output O;
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assign O = I;
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endmodule
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module BUFGSR(I, O);
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input I;
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output O;
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assign O = I;
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endmodule
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module BUFGTS(I, O);
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input I;
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output O;
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assign O = I;
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endmodule
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module FDDCP (C, PRE, CLR, D, Q);
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parameter INIT = 0;
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input C, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q <= 0;
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else if (PRE == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module FTCP (C, PRE, CLR, T, Q);
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parameter INIT = 0;
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input C, PRE, CLR, T;
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output wire Q;
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reg Q_;
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initial begin
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Q_ <= INIT;
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end
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always @(posedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q_ <= 0;
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else if (PRE == 1)
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Q_ <= 1;
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else if (T == 1)
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Q_ <= ~Q_;
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end
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assign Q = Q_;
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endmodule
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module FTCP_N (C, PRE, CLR, T, Q);
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parameter INIT = 0;
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input C, PRE, CLR, T;
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output wire Q;
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reg Q_;
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initial begin
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Q_ <= INIT;
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end
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always @(negedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q_ <= 0;
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else if (PRE == 1)
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Q_ <= 1;
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else if (T == 1)
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Q_ <= ~Q_;
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end
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assign Q = Q_;
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endmodule
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module FTDCP (C, PRE, CLR, T, Q);
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parameter INIT = 0;
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input C, PRE, CLR, T;
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output wire Q;
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reg Q_;
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initial begin
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Q_ <= INIT;
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end
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always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
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if (CLR == 1)
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Q_ <= 0;
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else if (PRE == 1)
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Q_ <= 1;
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else if (T == 1)
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Q_ <= ~Q_;
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end
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assign Q = Q_;
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endmodule
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@ -0,0 +1,156 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Coolrunner2SopPass : public Pass {
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Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
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virtual void help()
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{
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log("\n");
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log(" coolrunner2_sop [options] [selection]\n");
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log("\n");
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log("Break $sop cells into ANDTERM/ORTERM cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
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extra_args(args, 1, design);
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// Find all the $_NOT_ cells
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$_NOT_")
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{
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auto not_input = cell->getPort("\\A")[0];
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auto not_output = cell->getPort("\\Y")[0];
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not_cells[not_input] = {not_output, cell};
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}
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}
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}
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pool<tuple<Module*, Cell*>> cells_to_remove;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$sop")
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{
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// Read the inputs/outputs/parameters of the $sop cell
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auto sop_inputs = sigmap(cell->getPort("\\A"));
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auto sop_output = sigmap(cell->getPort("\\Y"))[0];
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auto sop_depth = cell->getParam("\\DEPTH").as_int();
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auto sop_width = cell->getParam("\\WIDTH").as_int();
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auto sop_table = cell->getParam("\\TABLE");
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// Check for a $_NOT_ at the output
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bool has_invert = false;
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if (not_cells.count(sop_output))
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{
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auto not_cell = not_cells.at(sop_output);
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has_invert = true;
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sop_output = std::get<0>(not_cell);
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// remove the $_NOT_ cell because it gets folded into the xor
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cells_to_remove.insert({module, std::get<1>(not_cell)});
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}
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// Construct AND cells
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pool<SigBit> intermed_wires;
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for (int i = 0; i < sop_depth; i++) {
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// Wire for the output
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auto and_out = module->addWire(NEW_ID);
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intermed_wires.insert(and_out);
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// Signals for the inputs
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pool<SigBit> and_in_true;
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pool<SigBit> and_in_comp;
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||||
for (int j = 0; j < sop_width; j++)
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{
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||||
if (sop_table[2 * (i * sop_width + j) + 0])
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{
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||||
and_in_comp.insert(sop_inputs[j]);
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||||
}
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||||
if (sop_table[2 * (i * sop_width + j) + 1])
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||||
{
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and_in_true.insert(sop_inputs[j]);
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||||
}
|
||||
}
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||||
|
||||
// Construct the cell
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auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
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||||
and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
|
||||
and_cell->setPort("\\OUT", and_out);
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||||
and_cell->setPort("\\IN", and_in_true);
|
||||
and_cell->setPort("\\IN_B", and_in_comp);
|
||||
}
|
||||
|
||||
if (sop_depth == 1)
|
||||
{
|
||||
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
|
||||
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
|
||||
xor_cell->setParam("\\INVERT_OUT", has_invert);
|
||||
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
|
||||
xor_cell->setPort("\\OUT", sop_output);
|
||||
}
|
||||
else
|
||||
{
|
||||
// Wire from OR to XOR
|
||||
auto or_to_xor_wire = module->addWire(NEW_ID);
|
||||
|
||||
// Construct the OR cell
|
||||
auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
|
||||
or_cell->setParam("\\WIDTH", sop_depth);
|
||||
or_cell->setPort("\\IN", intermed_wires);
|
||||
or_cell->setPort("\\OUT", or_to_xor_wire);
|
||||
|
||||
// Construct the XOR cell
|
||||
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
|
||||
xor_cell->setParam("\\INVERT_OUT", has_invert);
|
||||
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
|
||||
xor_cell->setPort("\\OUT", sop_output);
|
||||
}
|
||||
|
||||
// Finally, remove the $sop cell
|
||||
cells_to_remove.insert({module, cell});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Actually do the removal now that we aren't iterating
|
||||
for (auto mod_and_cell : cells_to_remove)
|
||||
{
|
||||
std::get<0>(mod_and_cell)->remove(std::get<1>(mod_and_cell));
|
||||
}
|
||||
}
|
||||
} Coolrunner2SopPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthCoolrunner2Pass : public ScriptPass
|
||||
{
|
||||
SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
|
||||
|
||||
virtual void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_coolrunner2 [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
|
||||
log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
|
||||
log("place-and-route.\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module (default='top')\n");
|
||||
log("\n");
|
||||
log(" -json <file>\n");
|
||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
||||
log(" is omitted if this parameter is not specified.\n");
|
||||
log("\n");
|
||||
log(" -run <from_label>:<to_label>\n");
|
||||
log(" only run the commands between the labels (see below). an empty\n");
|
||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -noflatten\n");
|
||||
log(" do not flatten design before synthesis\n");
|
||||
log("\n");
|
||||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, json_file;
|
||||
bool flatten, retime;
|
||||
|
||||
virtual void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
json_file = "";
|
||||
flatten = true;
|
||||
retime = false;
|
||||
}
|
||||
|
||||
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
string run_from, run_to;
|
||||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
||||
json_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noflatten") {
|
||||
flatten = false;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-retime") {
|
||||
retime = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This comannd only operates on fully selected designs!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
|
||||
virtual void script() YS_OVERRIDE
|
||||
{
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib +/coolrunner2/cells_sim.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
if (flatten && check_label("flatten", "(unless -noflatten)"))
|
||||
{
|
||||
run("proc");
|
||||
run("flatten");
|
||||
run("tribuf -logic");
|
||||
}
|
||||
|
||||
if (check_label("coarse"))
|
||||
{
|
||||
run("synth -run coarse");
|
||||
}
|
||||
|
||||
if (check_label("fine"))
|
||||
{
|
||||
run("opt -fast -full");
|
||||
run("techmap");
|
||||
run("techmap -map +/coolrunner2/cells_latch.v");
|
||||
run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
|
||||
}
|
||||
|
||||
if (check_label("map_pla"))
|
||||
{
|
||||
run("abc -sop -I 40 -P 56");
|
||||
run("coolrunner2_sop");
|
||||
run("opt -fast");
|
||||
}
|
||||
|
||||
if (check_label("map_cells"))
|
||||
{
|
||||
run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
|
||||
run("dffinit -ff FDCP Q INIT");
|
||||
run("dffinit -ff FDCP_N Q INIT");
|
||||
run("dffinit -ff LDCP Q INIT");
|
||||
run("dffinit -ff LDCP_N Q INIT");
|
||||
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
|
||||
}
|
||||
|
||||
if (check_label("check"))
|
||||
{
|
||||
run("hierarchy -check");
|
||||
run("stat");
|
||||
run("check -noinit");
|
||||
}
|
||||
|
||||
if (check_label("json"))
|
||||
{
|
||||
if (!json_file.empty() || help_mode)
|
||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
||||
}
|
||||
|
||||
log_pop();
|
||||
}
|
||||
} SynthCoolrunner2Pass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
library(xc2_dff) {
|
||||
cell(FDCP) {
|
||||
area: 1;
|
||||
ff("IQ", "IQN") { clocked_on: C;
|
||||
next_state: D;
|
||||
clear: "CLR";
|
||||
preset: "PRE"; }
|
||||
pin(C) { direction: input;
|
||||
clock: true; }
|
||||
pin(D) { direction: input; }
|
||||
pin(Q) { direction: output;
|
||||
function: "IQ"; }
|
||||
pin(CLR) { direction: input; }
|
||||
pin(PRE) { direction: input; }
|
||||
}
|
||||
|
||||
cell(FDCP_N) {
|
||||
area: 1;
|
||||
ff("IQ", "IQN") { clocked_on: "!C";
|
||||
next_state: D;
|
||||
clear: "CLR";
|
||||
preset: "PRE"; }
|
||||
pin(C) { direction: input;
|
||||
clock: true; }
|
||||
pin(D) { direction: input; }
|
||||
pin(Q) { direction: output;
|
||||
function: "IQ"; }
|
||||
pin(CLR) { direction: input; }
|
||||
pin(PRE) { direction: input; }
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue