mirror of https://github.com/YosysHQ/yosys.git
Added iCE40 const folding support for SB_CARRY
This commit is contained in:
Clifford Wolf
parent
752851954b
commit
8d4a675f91
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@ -1,6 +1,7 @@
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OBJS += techlibs/ice40/synth_ice40.o
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OBJS += techlibs/ice40/ice40_ffssr.o
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OBJS += techlibs/ice40/ice40_opt.o
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GENFILES += techlibs/ice40/brams_init1.vh
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GENFILES += techlibs/ice40/brams_init2.vh
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@ -0,0 +1,131 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void run_ice40_opts(Module *module)
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\SB_CARRY")
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{
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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SigBit inbit[3] = {cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\CI")};
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for (int i = 0; i < 3; i++)
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if (inbit[i].wire == nullptr) {
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if (inbit[i] == State::S1)
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count_ones++;
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else
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count_zeros++;
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} else
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non_const_inputs.append(inbit[i]);
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if (count_zeros >= 2)
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replacement_output = State::S0;
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if (count_ones >= 2)
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replacement_output = State::S1;
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if (GetSize(non_const_inputs) == 1)
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replacement_output = non_const_inputs;
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if (GetSize(replacement_output)) {
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module->connect(cell->getPort("\\CO"), replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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module->remove(cell);
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continue;
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}
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}
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}
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}
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struct Ice40OptPass : public Pass {
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Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_opt [options] [selection]\n");
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log("\n");
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log("This command executes the following script:\n");
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log("\n");
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log(" do\n");
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log(" <ice40 specific optimizations>\n");
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log(" opt_const -mux_undef -undriven [-full]\n");
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log(" opt_share\n");
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log(" opt_rmdff\n");
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log(" opt_clean\n");
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log(" while <changed design>\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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string opt_const_args = "-mux_undef -undriven";
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log_header("Executing ICE40_OPT pass (performing simple optimizations).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-full") {
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opt_const_args += " -full";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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while (1)
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{
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design->scratchpad_unset("opt.did_something");
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log_header("Running ICE40 specific optimizations.\n");
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for (auto module : design->selected_modules())
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run_ice40_opts(module);
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Pass::call(design, "opt_const " + opt_const_args);
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Pass::call(design, "opt_share");
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean");
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if (design->scratchpad_get_bool("opt.did_something") == false)
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break;
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log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
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}
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design->optimize();
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design->sort();
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design->check();
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log_header("Finished OPT passes. (There is nothing left to do.)\n");
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log_pop();
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}
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} Ice40OptPass;
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PRIVATE_NAMESPACE_END
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@ -198,7 +198,7 @@ struct SynthIce40Pass : public Pass {
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Pass::call(design, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
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if (retime)
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Pass::call(design, "abc -dff");
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Pass::call(design, "opt -fast");
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Pass::call(design, "ice40_opt");
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}
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if (check_label(active, run_from, run_to, "map_ffs"))
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@ -208,7 +208,7 @@ struct SynthIce40Pass : public Pass {
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Pass::call(design, "opt_const -mux_undef");
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Pass::call(design, "simplemap");
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Pass::call(design, "ice40_ffssr");
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Pass::call(design, "clean");
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Pass::call(design, "ice40_opt -full");
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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