riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Indenting fixes in gowin sim cell lib

This commit is contained in:
Clifford Wolf 2016-11-08 18:54:00 +01:00
parent 97ac77513f
commit e9d73d2ee0
1 changed files with 28 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
techlibs/gowin/cells_sim.v
View File

@ -1,51 +1,59 @@
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
assign F = I0 ? INIT[1] : INIT[0];
parameter [1:0] INIT = 0;
assign F = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
module DFF (output reg Q, input CLK, D);
always @(posedge C)
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK)
Q <= D;
endmodule
module DFFN (output reg Q, input CLK, D);
always @(negedge C)
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge CLK)
Q <= D;
endmodule
module VCC(output V);
assign V = 1;
assign V = 1;
endmodule
module GND(output G);
assign G = 0;
assign G = 0;
endmodule
module IBUF(output O, input I);
assign O = I;
assign O = I;
endmodule
module OBUF(output O, input I);
assign O = I;
assign O = I;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule