riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Tiny bugfix in simlib.v

This commit is contained in:
Clifford Wolf 2013-03-26 19:06:28 +01:00
parent 7a99349de4
commit 26f2439551
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
techlibs/simlib.v
View File

@ -646,7 +646,6 @@ module \$sr (S, R, Q);
parameter WIDTH = 0;
input CLK;
input [WIDTH-1:0] S, R;
output reg [WIDTH-1:0] Q;