riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Improvements and bugfixes for generate blocks with local signals

This commit is contained in:
Clifford Wolf 2013-03-26 11:13:58 +01:00
parent 6a382f2aba
commit 7a99349de4
2 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/ast/simplify.cc
View File

@ -896,10 +896,8 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
return;
}
if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0) {
if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0)
str = name_map[str];
return;
}
std::map<std::string, std::string> backup_name_map;

2
frontends/verilog/lexer.l
View File

@ -184,7 +184,7 @@ supply1 { return TOK_SUPPLY1; }
"$signed" { return TOK_TO_SIGNED; }
"$unsigned" { return TOK_TO_UNSIGNED; }
[a-zA-Z_$][a-zA-Z0-9_$]* {
[a-zA-Z_$][a-zA-Z0-9_\.$]* {
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_ID;
}