mirror of https://github.com/YosysHQ/yosys.git
Added "synth -nordff -noalumacc"
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@ -58,6 +58,13 @@ struct SynthPass : public Pass {
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log(" -noabc\n");
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log(" do not run abc (as if yosys was compiled without ABC support)\n");
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log("\n");
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log(" -noalumacc\n");
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log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
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log(" their direct form ($add, $sub, etc.).\n");
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log("\n");
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log(" -nordff\n");
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log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
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log("\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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@ -102,8 +109,9 @@ struct SynthPass : public Pass {
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module, fsm_opts;
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std::string top_module, fsm_opts, memory_opts;
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std::string run_from, run_to;
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bool noalumacc = false;
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bool noabc = false;
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size_t argidx;
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@ -132,6 +140,14 @@ struct SynthPass : public Pass {
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noabc = true;
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continue;
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}
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if (args[argidx] == "-noalumacc") {
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noalumacc = true;
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continue;
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}
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if (args[argidx] == "-nordff") {
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memory_opts += " -nordff";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -159,12 +175,13 @@ struct SynthPass : public Pass {
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Pass::call(design, "check");
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Pass::call(design, "opt");
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Pass::call(design, "wreduce");
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Pass::call(design, "alumacc");
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if (!noalumacc)
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Pass::call(design, "alumacc");
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Pass::call(design, "share");
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Pass::call(design, "opt");
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Pass::call(design, "fsm" + fsm_opts);
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Pass::call(design, "opt -fast");
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Pass::call(design, "memory -nomap");
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Pass::call(design, "memory -nomap" + memory_opts);
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Pass::call(design, "opt_clean");
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}
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