riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

greenpak4: Added POUT to GP_COUNTx cells

This commit is contained in:
Andrew Zonenberg 2017-01-01 00:56:20 -08:00
parent 5ffede5c0e
commit 27a626ce98
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
techlibs/greenpak4/cells_sim.v
View File

@ -53,7 +53,7 @@ module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
module GP_COUNT8(input CLK, input wire RST, output reg OUT);
module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
@ -67,6 +67,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
//Combinatorially output whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
OUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@ -103,7 +104,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP);
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
@ -116,7 +117,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP);
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";