mirror of https://github.com/YosysHQ/yosys.git
Added GreenPak inverter support
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@ -33,8 +33,13 @@ module \$lut (A, Y);
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generate
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if (WIDTH == 1) begin
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GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(1'b0));
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if(LUT == 2'b01) begin
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GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
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end
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else begin
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GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(1'b0));
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end
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end else
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if (WIDTH == 2) begin
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GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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@ -40,6 +40,10 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q);
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end
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endmodule
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module GP_INV(input IN, output OUT);
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assign OUT = ~IN;
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endmodule
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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@ -207,8 +207,8 @@ struct SynthGreenPAK4Pass : public Pass {
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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if (part == "SLG46140V") Pass::call(design, "nlutmap -luts 0,6,8,2");
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if (part == "SLG46620V") Pass::call(design, "nlutmap -luts 0,8,16,2");
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if (part == "SLG46621V") Pass::call(design, "nlutmap -luts 0,8,16,2");
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if (part == "SLG46620V") Pass::call(design, "nlutmap -luts 2,8,16,2");
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if (part == "SLG46621V") Pass::call(design, "nlutmap -luts 2,8,16,2");
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Pass::call(design, "clean");
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}
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