mirror of https://github.com/YosysHQ/yosys.git
Improvements in synth_greenpak4, added -part option
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@ -47,12 +47,12 @@ struct SynthGreenPAK4Pass : public Pass {
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log(" -part <part>\n");
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log(" synthesize for the specified part. Valid values are SLG46140V,\n");
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log(" SLG46620V, and SLG46621V (default).\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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@ -91,7 +91,9 @@ struct SynthGreenPAK4Pass : public Pass {
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log(" abc -dff (only if -retime)\n");
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log("\n");
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log(" map_luts:\n");
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log(" nlutmap -luts 0,8,16,2\n");
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log(" nlutmap -luts 0,6,8,2 (for -part SLG46140V)\n");
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log(" nlutmap -luts 0,8,16,2 (for -part SLG46620V)\n");
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log(" nlutmap -luts 0,8,16,2 (for -part SLG46621V)\n");
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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@ -103,18 +105,16 @@ struct SynthGreenPAK4Pass : public Pass {
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log(" stat\n");
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log(" check -noinit\n");
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log("\n");
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log(" blif:\n");
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log(" write_blif -gates -attr -param <file-name>\n");
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log("\n");
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log(" edif:\n");
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log(" write_edif <file-name>\n");
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log(" json:\n");
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log(" write_json <file-name>\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_opt = "-auto-top";
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std::string part = "SLG46621V";
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std::string run_from, run_to;
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std::string blif_file, edif_file;
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std::string json_file;
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bool flatten = true;
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bool retime = false;
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@ -125,12 +125,12 @@ struct SynthGreenPAK4Pass : public Pass {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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if (args[argidx] == "-part" && argidx+1 < args.size()) {
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part = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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@ -141,10 +141,6 @@ struct SynthGreenPAK4Pass : public Pass {
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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@ -160,6 +156,9 @@ struct SynthGreenPAK4Pass : public Pass {
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
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log_cmd_error("Invalid part name: '%s'\n", part.c_str());
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bool active = run_from.empty();
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log_header("Executing SYNTH_GREENPAK4 pass.\n");
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@ -197,7 +196,9 @@ struct SynthGreenPAK4Pass : public Pass {
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "nlutmap -luts 0,8,16,2");
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if (part == "SLG46140V") Pass::call(design, "nlutmap -luts 0,6,8,2");
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if (part == "SLG46620V") Pass::call(design, "nlutmap -luts 0,8,16,2");
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if (part == "SLG46621V") Pass::call(design, "nlutmap -luts 0,8,16,2");
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Pass::call(design, "clean");
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}
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@ -214,16 +215,10 @@ struct SynthGreenPAK4Pass : public Pass {
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Pass::call(design, "check -noinit");
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}
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if (check_label(active, run_from, run_to, "blif"))
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if (check_label(active, run_from, run_to, "json"))
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{
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if (!blif_file.empty())
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Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
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}
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if (check_label(active, run_from, run_to, "edif"))
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{
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if (!edif_file.empty())
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Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
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if (!json_file.empty())
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Pass::call(design, stringf("write_json %s", json_file.c_str()));
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}
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log_pop();
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