riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Changed order of passes for better handling of INIT attributes on "output reg" FFs

This commit is contained in:
Andrew Zonenberg 2016-05-04 17:13:54 -07:00
parent 3486637b19
commit 2096a05ec2
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/greenpak4/synth_greenpak4.cc
View File

@ -176,13 +176,13 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("map_cells"))
{
run("shregmap -tech greenpak4");
run("iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO");
run("dfflibmap -liberty +/greenpak4/gp_dff.lib");
run("techmap -map +/greenpak4/cells_map.v");
run("dffinit -ff GP_DFF Q INIT");
run("dffinit -ff GP_DFFR Q INIT");
run("dffinit -ff GP_DFFS Q INIT");
run("dffinit -ff GP_DFFSR Q INIT");
run("iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO");
run("techmap -map +/greenpak4/cells_map.v");
run("clean");
}