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Added final checks to "synth" and "synth_xilinx"

This commit is contained in:
Clifford Wolf 2015-02-15 13:00:00 +01:00
parent 40f021e136
commit 881dcd8af9
2 changed files with 24 additions and 7 deletions
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21
techlibs/common/synth.cc
View File

@ -90,12 +90,14 @@ struct SynthPass : public Pass {
log(" techmap\n");
log(" opt -fast\n");
#ifdef YOSYS_ENABLE_ABC
log("\n");
log(" abc:\n");
log(" abc -fast\n");
log(" opt -fast\n");
#endif
log("\n");
log(" check:\n");
log(" hierarchy -check\n");
log(" check\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
@ -172,15 +174,20 @@ struct SynthPass : public Pass {
Pass::call(design, "opt -full");
Pass::call(design, "techmap");
Pass::call(design, "opt -fast");
if (!noabc) {
#ifdef YOSYS_ENABLE_ABC
Pass::call(design, "abc -fast");
Pass::call(design, "opt -fast");
#endif
}
}
#ifdef YOSYS_ENABLE_ABC
if (check_label(active, run_from, run_to, "abc") && !noabc)
if (check_label(active, run_from, run_to, "check"))
{
Pass::call(design, "abc -fast");
Pass::call(design, "opt -fast");
Pass::call(design, "hierarchy -check");
Pass::call(design, "check");
}
#endif
log_pop();
}

10
techlibs/xilinx/synth_xilinx.cc
View File

@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass {
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log("\n");
log(" check:\n");
log(" hierarchy -check\n");
log(" check -noinit\n");
log("\n");
log(" edif:\n");
log(" write_edif synth.edif\n");
log("\n");
@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "clean");
}
if (check_label(active, run_from, run_to, "check"))
{
Pass::call(design, "hierarchy -check");
Pass::call(design, "check -noinit");
}
if (check_label(active, run_from, run_to, "edif"))
{
if (!edif_file.empty())