mirror of https://github.com/YosysHQ/yosys.git
Added very first version of "synth_ice40"
This commit is contained in:
Clifford Wolf
parent
ed15400fc6
commit
42d5d94a5d
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OBJS += techlibs/ice40/synth_ice40.o
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
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module \$_DFF_P_ (input D, C, output Q);
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SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C));
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
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end else
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if (WIDTH == 2) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
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end else
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if (WIDTH == 3) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
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end else
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if (WIDTH == 4) begin
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SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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module SB_LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module SB_DFF (output reg Q, input C, D);
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always @(posedge C)
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Q <= D;
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endmodule
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
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{
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if (label == run_from)
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active = true;
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if (label == run_to)
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active = false;
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return active;
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}
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struct SynthIce40Pass : public Pass {
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SynthIce40Pass() : Pass("synth_ice40", "synthesis for iCE40 FPGAs") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_ice40 [options]\n");
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log("\n");
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log("This command runs synthesis for iCE40 FPGAs. This work is experimental.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("\n");
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log(" begin:\n");
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log(" read_verilog -lib +/ice40/cells_sim.v\n");
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log(" hierarchy -check -top <top>\n");
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log("\n");
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log(" coarse:\n");
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log(" synth -run coarse\n");
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log("\n");
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log(" fine:\n");
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log(" opt -fast -full\n");
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log(" memory_map\n");
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log(" opt -full\n");
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log(" techmap\n");
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log(" opt -fast\n");
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log("\n");
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log(" map_luts:\n");
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log(" abc -lut 4\n");
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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log(" techmap -map +/ice40/cells_map.v\n");
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log(" clean\n");
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log("\n");
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log(" check:\n");
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log(" hierarchy -check\n");
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log(" stat\n");
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log(" check -noinit\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module = "top";
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std::string run_from, run_to;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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bool active = run_from.empty();
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log_header("Executing SYNTH_ICE40 pass.\n");
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log_push();
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if (check_label(active, run_from, run_to, "begin"))
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{
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Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v");
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Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
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}
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if (check_label(active, run_from, run_to, "coarse"))
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{
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Pass::call(design, "synth -run coarse");
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}
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if (check_label(active, run_from, run_to, "fine"))
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{
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Pass::call(design, "opt -fast -full");
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Pass::call(design, "memory_map");
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Pass::call(design, "opt -full");
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Pass::call(design, "techmap");
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Pass::call(design, "opt -fast");
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -lut 4");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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Pass::call(design, "techmap -map +/ice40/cells_map.v");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "check"))
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{
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Pass::call(design, "hierarchy -check");
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Pass::call(design, "stat");
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Pass::call(design, "check -noinit");
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}
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log_pop();
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}
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} SynthIce40Pass;
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PRIVATE_NAMESPACE_END
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