mirror of https://github.com/YosysHQ/yosys.git
Replaced $__alu CO/CS outputs with full-width CO output
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Clifford Wolf
parent
3a7d5d188d
commit
eb571cba6a
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@ -251,19 +251,18 @@ endmodule
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// ALU Infrastructure
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// --------------------------------------------------------
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module \$__alu_ripple (A, B, CI, X, Y, CO, CS);
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module \$__alu_ripple (A, B, CI, X, Y, CO);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] X, Y;
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input CI;
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output CO, CS;
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output [WIDTH-1:0] CO;
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wire [WIDTH:0] carry;
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assign carry[0] = CI;
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assign CO = carry[WIDTH];
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assign CS = carry[WIDTH-1];
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assign CO = carry[WIDTH:1];
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genvar i;
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generate
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@ -291,7 +290,7 @@ module \$__lcu (P, G, CI, CO);
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input [WIDTH-1:0] P, G;
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input CI;
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output reg [WIDTH:0] CO;
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output [WIDTH-1:0] CO;
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integer i, j;
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reg [WIDTH-1:0] p, g;
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@ -326,23 +325,20 @@ module \$__lcu (P, G, CI, CO);
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end
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end
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assign CO = {g, CI};
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assign CO = g;
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endmodule
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module \$__alu_lookahead (A, B, CI, X, Y, CO, CS);
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module \$__alu_lookahead (A, B, CI, X, Y, CO);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] X, Y;
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input CI;
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output CO, CS;
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output [WIDTH-1:0] CO;
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wire [WIDTH-1:0] P, G;
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wire [WIDTH:0] C;
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assign CO = C[WIDTH];
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assign CS = C[WIDTH-1];
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wire [WIDTH:0] carry;
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genvar i;
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generate
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@ -354,15 +350,16 @@ module \$__alu_lookahead (A, B, CI, X, Y, CO, CS);
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\$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
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\$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
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assign a = A[i], b = B[i], c = C[i];
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assign a = A[i], b = B[i], c = carry[i];
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assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
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end
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endgenerate
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\$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
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\$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
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assign carry = {CO, CI};
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endmodule
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module \$__alu (A, B, CI, BI, X, Y, CO, CS);
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module \$__alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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@ -375,19 +372,19 @@ module \$__alu (A, B, CI, BI, X, Y, CO, CS);
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// carry in, sub, carry out, carry sign
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input CI, BI;
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output CO, CS;
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output [Y_WIDTH-1:0] CO;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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`ifdef ALU_RIPPLE
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
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`else
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if (Y_WIDTH <= 4) begin
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
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\$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
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end else begin
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\$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
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\$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
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end
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`endif
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endmodule
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@ -397,7 +394,7 @@ endmodule
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// ALU Cell Types: Compare, Add, Subtract
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// --------------------------------------------------------
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`define ALU_COMMONS(_width, _ci, _bi) """
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`define ALU_COMMONS(_width, _sub) """
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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@ -410,8 +407,8 @@ endmodule
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire alu_co, alu_cs;
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wire [WIDTH-1:0] alu_x, alu_y;
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wire [WIDTH-1:0] alu_x, alu_y, alu_co;
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wire [WIDTH:0] carry = {alu_co, |_sub};
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\$__alu #(
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.A_SIGNED(A_SIGNED),
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@ -422,41 +419,40 @@ endmodule
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) alu (
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.A(A),
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.B(B),
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.CI(_ci),
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.BI(_bi),
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.CI(|_sub),
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.BI(|_sub),
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.X(alu_x),
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.Y(alu_y),
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.CO(alu_co),
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.CS(alu_cs)
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.CO(alu_co)
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);
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wire cf, of, zf, sf;
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assign cf = !alu_co;
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assign of = alu_co ^ alu_cs;
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assign cf = !carry[WIDTH];
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assign of = carry[WIDTH] ^ carry[WIDTH-1];
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assign sf = alu_y[WIDTH-1];
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"""
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module \$lt (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
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assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
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endmodule
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module \$le (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
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assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
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endmodule
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module \$add (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(Y_WIDTH, 0, 0)
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`ALU_COMMONS(Y_WIDTH, 0)
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assign Y = alu_y;
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endmodule
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module \$sub (A, B, Y);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(Y_WIDTH, 1, 1)
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`ALU_COMMONS(Y_WIDTH, 1)
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assign Y = alu_y;
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endmodule
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