Added comment to clarify GP_ABUF cell

2016-05-02 20:29:39 -07:00 · 2016-05-02 20:29:39 -07:00 · 9fc9d5f1fb
parent 79460208c9
commit 9fc9d5f1fb
1 changed files with 2 additions and 0 deletions
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@ -17,6 +17,8 @@ module GP_ABUF(input wire IN, output wire OUT);
 	
 	assign OUT = IN;
 	
+	//cannot simulate mixed signal IP
+	
 endmodule

 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);