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Added $bu0 cell to simlib.v

This commit is contained in:
Clifford Wolf 2014-01-18 15:35:15 +01:00
parent 839af272ad
commit 5b96675696
1 changed files with 22 additions and 0 deletions
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22
techlibs/common/simlib.v
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@ -53,6 +53,28 @@ assign Y = ~A_BUF.val;
endmodule
// --------------------------------------------------------
module \$bu0 (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
`INPUT_A
output [Y_WIDTH-1:0] Y;
generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
assign Y[A_WIDTH-1:0] = A_BUF.val;
assign Y[Y_WIDTH-1:A_WIDTH] = 0;
end else begin:B
assign Y = +A_BUF.val;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$pos (A, Y);