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More fixes for bugs found using xsthammer

This commit is contained in:
Clifford Wolf 2013-06-13 11:18:45 +02:00
parent b1d39aa865
commit 0c6ffc4c65
5 changed files with 24 additions and 16 deletions
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6
frontends/ast/genrtlil.cc
View File

@ -752,7 +752,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint);
is_signed = type == AST_NEG || (type == AST_POS && children[0]->is_signed);
int width = type == AST_NEG && arg.width < width_hint ? arg.width+1 : arg.width;
if (width > width_hint && width_hint > 0)
if (width_hint > 0)
width = width_hint;
return uniop2rtlil(this, type_name, width, arg);
}
@ -766,9 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
int width = std::max(left.width, right.width);
if (width > width_hint && width_hint > 0)
width = width_hint;
if (width < width_hint)
if (width_hint > 0)
width = width_hint;
return binop2rtlil(this, type_name, width, left, right);
}

4
frontends/verilog/lexer.l
View File

@ -236,8 +236,8 @@ supply1 { return TOK_SUPPLY1; }
"===" { return OP_EQ; }
"!==" { return OP_NE; }
/* "~&" { return OP_NAND; } */
/* "~|" { return OP_NOR; } */
"~&" { return OP_NAND; }
"~|" { return OP_NOR; }
"~^" { return OP_XNOR; }
"^~" { return OP_XNOR; }

14
frontends/verilog/parser.y
View File

@ -113,9 +113,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
// operator precedence from low to high
%left OP_LOR
%left OP_LAND
%left '|'
%left '|' OP_NOR
%left '^' OP_XNOR
%left '&'
%left '&' OP_NAND
%left OP_EQ OP_NE
%left '<' OP_LE OP_GE '>'
%left OP_SHL OP_SHR OP_SSHL OP_SSHR
@ -982,10 +982,20 @@ basic_expr:
$$ = new AstNode(AST_REDUCE_AND, $3);
append_attr($$, $2);
} |
OP_NAND attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_AND, $3);
append_attr($$, $2);
$$ = new AstNode(AST_LOGIC_NOT, $$);
} |
'|' attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_OR, $3);
append_attr($$, $2);
} |
OP_NOR attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_OR, $3);
append_attr($$, $2);
$$ = new AstNode(AST_LOGIC_NOT, $$);
} |
'^' attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_XOR, $3);
append_attr($$, $2);

1
kernel/satgen.h
View File

@ -128,6 +128,7 @@ struct SatGen
if (cell->type == "$_INV_" || cell->type == "$not") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
extendSignalWidthUnary(a, y, cell);
ez->assume(ez->vec_eq(ez->vec_not(a), y));
return true;
}

15
techlibs/stdcells.v
View File

@ -41,17 +41,16 @@ parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
if (i < A_WIDTH) begin
\$_INV_ gate (
.A(A[i]),
.Y(Y[i])
);
end else begin
assign Y[i] = 0;
end
\$_INV_ gate (
.A(A_buf[i]),
.Y(Y[i])
);
end
endgenerate