Merge branch 'master' of github.com:cliffordwolf/yosys

This commit is contained in:
Clifford Wolf 2013-06-12 19:31:17 +02:00
commit b1d39aa865
5 changed files with 81 additions and 5 deletions

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@ -24,6 +24,9 @@
#include <stdlib.h>
#include <assert.h>
const int ezSAT::TRUE = 1;
const int ezSAT::FALSE = 2;
ezSAT::ezSAT()
{
literal("TRUE");

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@ -44,8 +44,8 @@ public:
OpNot, OpAnd, OpOr, OpXor, OpIFF, OpITE
};
const int TRUE = 1;
const int FALSE = 2;
static const int TRUE;
static const int FALSE;
private:
std::map<std::string, int> literalsCache;

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@ -2,3 +2,4 @@
OBJS += passes/cmds/select.o
OBJS += passes/cmds/show.o
OBJS += passes/cmds/rename.o
OBJS += passes/cmds/scatter.o

72
passes/cmds/scatter.cc Normal file
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@ -0,0 +1,72 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" scatter [selection]\n");
log("\n");
log("This command adds additional intermediate nets on all cell ports. This is used\n");
log("for testing the correct use of the SigMap halper in passes. If you don't know\n");
log("what this means: don't worry -- you only need this pass when testing your own\n");
log("extensions to Yosys.\n");
log("\n");
log("Use the opt_clean command to get rid of the additional nets.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
CellTypes ct(design);
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
{
if (!design->selected(mod_it.second))
continue;
for (auto &c : mod_it.second->cells)
for (auto &p : c.second->connections)
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = NEW_ID;
wire->width = p.second.width;
mod_it.second->add(wire);
if (ct.cell_output(c.second->type, p.first)) {
RTLIL::SigSig sigsig(p.second, wire);
mod_it.second->connections.push_back(sigsig);
} else {
RTLIL::SigSig sigsig(wire, p.second);
mod_it.second->connections.push_back(sigsig);
}
p.second = wire;
}
}
}
} ScatterPass;

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@ -517,7 +517,7 @@ struct ShowPass : public Pass {
log(" more than one library.\n");
log("\n");
log(" -prefix <prefix>\n");
log(" generate <prefix>.dot and <prefix>.ps instead of yosys-show.{dot,ps}\n");
log(" generate <prefix>.dot and <prefix>.ps instead of ~/.yosys_show.{dot,ps}\n");
log("\n");
log(" -color <color> <wire>\n");
log(" assign the specified color to the specified wire. The object can be\n");
@ -539,7 +539,7 @@ struct ShowPass : public Pass {
log("When no <format> is specified, SVG is used. When no <format> and <viewer> is\n");
log("specified, 'yosys-svgviewer' is used to display the schematic.\n");
log("\n");
log("The generated output files are 'yosys-show.dot' and 'yosys-show.<format>',\n");
log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n");
log("unless another prefix is specified using -prefix <prefix>.\n");
log("\n");
}
@ -553,7 +553,7 @@ struct ShowPass : public Pass {
std::string format;
std::string viewer_exe;
std::string prefix = "yosys-show";
std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : ".");
std::vector<std::string> libfiles;
std::vector<RTLIL::Design*> libs;
uint32_t colorSeed = 0;