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greenpak4: Changed name of inverted output ports for consistency

This commit is contained in:
Andrew Zonenberg 2016-08-14 00:30:45 -07:00
parent 3b9756c6a3
commit 0b0ba96488
2 changed files with 19 additions and 19 deletions
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8
techlibs/greenpak4/cells_map.v
View File

@ -24,7 +24,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q);
);
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg Q);
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DFFSRI #(
.INIT(INIT),
@ -33,11 +33,11 @@ module GP_DFFSI(input D, CLK, nSET, output reg Q);
.D(D),
.CLK(CLK),
.nSR(nSET),
.Q(Q)
.nQ(nQ)
);
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg Q);
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
GP_DFFSRI #(
.INIT(INIT),
@ -46,7 +46,7 @@ module GP_DFFRI(input D, CLK, nRST, output reg Q);
.D(D),
.CLK(CLK),
.nSR(nRST),
.Q(Q)
.nQ(nQ)
);
endmodule

30
techlibs/greenpak4/cells_sim.v
View File

@ -165,11 +165,11 @@ module GP_DFF(input D, CLK, output reg Q);
end
endmodule
module GP_DFFI(input D, CLK, output reg Q);
module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(posedge CLK) begin
Q <= ~D;
nQ <= ~D;
end
endmodule
@ -184,14 +184,14 @@ module GP_DFFR(input D, CLK, nRST, output reg Q);
end
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg Q);
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b1;
nQ <= 1'b1;
else
Q <= ~D;
nQ <= ~D;
end
endmodule
@ -206,14 +206,14 @@ module GP_DFFS(input D, CLK, nSET, output reg Q);
end
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg Q);
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b0;
nQ <= 1'b0;
else
Q <= ~D;
nQ <= ~D;
end
endmodule
@ -229,15 +229,15 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q);
end
endmodule
module GP_DFFSRI(input D, CLK, nSR, output reg Q);
module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= ~SRMODE;
nQ <= ~SRMODE;
else
Q <= ~D;
nQ <= ~D;
end
endmodule