mirror of https://github.com/YosysHQ/yosys.git
Added GP_RCOSC cell
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@ -118,6 +118,44 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI
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endmodule
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module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter PRE_DIV = 1;
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parameter FABRIC_DIV = 1;
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parameter OSC_FREQ = "25k"
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initial CLKOUT_PREDIV = 0;
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initial CLKOUT_FABRIC = 0;
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//output dividers not implemented for simulation
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//auto powerdown not implemented for simulation
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always begin
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if(PWRDN) begin
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CLKOUT_PREDIV = 0;
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CLKOUT_FABRIC = 0;
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end
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else begin
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if(OSC_FREQ == "25k") begin
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//half period of 25 kHz
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#20000;
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end
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else begin
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//half period of 2 MHz
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#250;
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end
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CLKOUT_PREDIV = ~CLKOUT_PREDIV;
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CLKOUT_FABRIC = ~CLKOUT_FABRIC;
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end
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end
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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