Improved xilinx mojo_counter example

techlibs/xilinx7/example_mojo_counter/example.sh

@@ -19,11 +19,14 @@ abc -lut 6; opt
 # map internal cells to FPGA cells
 techmap -map ../cells.v; opt
 
+# insert i/o buffers
+iopadmap -outpad OBUF I:O -inpad BUFGP O:I
+
 # write netlist
 write_edif synth.edif
 EOT
 
-cat > synth.ut <<- EOT
+cat > bitgen.ut <<- EOT
 	-w
 	-g DebugBitstream:No
 	-g Binary:no

techlibs/xilinx7/example_mojo_counter/example.v

@@ -7,7 +7,7 @@ output led_3, led_2, led_1, led_0;
 reg [31:0] counter;
 
 always @(posedge clk)
-	counter <= counter + 1;
+	counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
 
 assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;