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Bugfix in simlib.v for iverilog

This commit is contained in:
Clifford Wolf 2014-07-29 19:23:31 +02:00
parent 77e2d39cd0
commit 2145e57ef0
1 changed files with 6 additions and 5 deletions
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11
techlibs/common/simlib.v
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@ -455,11 +455,12 @@ input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (B_SIGNED) begin:BLOCK1
assign Y = A[$signed(B) +: Y_WIDTH];
end else begin:BLOCK2
assign Y = A[B +: Y_WIDTH];
end
if (Y_WIDTH > 0)
if (B_SIGNED) begin:BLOCK1
assign Y = A[$signed(B) +: Y_WIDTH];
end else begin:BLOCK2
assign Y = A[B +: Y_WIDTH];
end
endgenerate
endmodule