Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
...
This reverts commit 2f427acc9e
.
2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
36d94caec1
Remove `shregmap -tech xilinx` additions
2019-08-22 11:22:09 -07:00
Eddie Hung
affe9c9c1a
Merge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-20 20:06:47 -07:00
Eddie Hung
fe61dcce8b
Grammar
2019-08-20 20:05:51 -07:00
Eddie Hung
193eae0c84
techmap -max_iter to apply to each module individually
2019-08-20 19:50:20 -07:00
Eddie Hung
57493e328a
techmap -max_iter to apply to each module individually
2019-08-20 19:48:16 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
fad15d276d
retime_mode -> dff_mode
2019-08-20 18:08:58 -07:00
Eddie Hung
505d062daf
Fix use of {CLK,EN}_POLARITY, also add a FIXME
2019-08-20 13:33:31 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
...
Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
1f03154a0c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 15:19:32 -07:00
Eddie Hung
e29df7d5fa
Remove debug
2019-08-19 12:44:43 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
7e010834eb
Fix typo
2019-08-19 10:41:18 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Eddie Hung
9bfe924e17
Set abc_flop and use it in toposort
2019-08-19 09:40:01 -07:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
...
Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
8915f496d9
Merge pull request #1300 from YosysHQ/eddie/cleanup2
...
Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
2019-08-17 15:01:31 +02:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
5abe133323
Use ID()
2019-08-16 16:38:49 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Eddie Hung
6b51c154c6
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-16 13:38:47 -07:00
Clifford Wolf
958be89c47
Merge pull request #1302 from mmicko/dfflibmap_regression
...
DFFLIBMAP pass regression fix
2019-08-16 14:26:58 +02:00
Miodrag Milanovic
72eacdb9f8
Regression in abc9
2019-08-16 13:21:11 +02:00
Miodrag Milanovic
bb79e050a5
Just needed IDs to be IdString
2019-08-16 11:50:34 +02:00
Clifford Wolf
bb37a20e8d
Add missing NMUX to "abc -g" handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 10:36:11 +02:00
Eddie Hung
eae5a6b12c
Use ID::keep more liberally too
2019-08-15 14:51:12 -07:00
Eddie Hung
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
Eddie Hung
02dead2e60
ID(\\.*) -> ID(.*)
2019-08-15 10:25:54 -07:00
Eddie Hung
78ba8b8574
Transform all "\\*" identifiers into ID()
2019-08-15 10:19:29 -07:00
Eddie Hung
9f98241010
Transform "$.*" to ID("$.*") in passes/techmap
2019-08-15 10:05:08 -07:00
Eddie Hung
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
Eddie Hung
1551e14d2d
AND with an inverted input, causes X{,N}OR output to be inverted too
2019-08-14 16:26:24 -07:00
Eddie Hung
1e47e81869
Revert "Only sort leaves on non-ANDNOT/ORNOT cells"
...
This reverts commit 5ec5f6dec7
.
2019-08-14 15:23:25 -07:00
Eddie Hung
5ec5f6dec7
Only sort leaves on non-ANDNOT/ORNOT cells
2019-08-14 11:25:56 -07:00
Eddie Hung
0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
2019-08-14 10:40:53 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
e4a0971581
Since $_ANDNOT_ is not symmetric, do not sort leaves
2019-08-12 11:17:15 -07:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
...
Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
6d0be8d206
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-09 19:17:59 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
58e512ab70
Add comment
2019-08-07 09:54:27 -07:00
Eddie Hung
f20acbc813
Revert "Add TODO"
...
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
2019-08-07 09:54:27 -07:00
Eddie Hung
789585a744
Add TODO
2019-08-07 09:54:27 -07:00
Eddie Hung
8a8c1d7857
Compute box_lookup just once
2019-08-07 09:54:27 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
100c377451
Redesign of cell cost API
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 01:12:14 +02:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix
...
Visual Studio build fix
2019-08-02 17:07:39 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
...
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
...
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Miodrag Milanovic
2b469e82a7
Fix check logic in extract_fa
2019-07-16 10:35:18 +02:00
Eddie Hung
9b91d815b5
If ConstEval fails do not log_abort() but return gracefully
2019-07-13 04:13:57 -07:00
Eddie Hung
fb062c3426
Add comment
2019-07-13 00:52:21 -07:00
Eddie Hung
e9bdc86c0e
duplicate -> clone
2019-07-12 19:33:02 -07:00
Eddie Hung
be0cb7f4b8
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7d583f9e57
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
83f23a24a8
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
1adbfb5533
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
39a7c7c54c
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
91c07be196
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
399e1ec870
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
58dbb28fd3
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7dc15bdd2d
Do not double count cells in abc
2019-07-12 08:22:26 -07:00
Eddie Hung
237d8651a5
Error out if abc9 not called with -lut or -luts
2019-07-11 09:58:00 -07:00
Eddie Hung
0c3ed73dad
Count $_NOT_ cells turned into $luts
2019-07-11 09:55:14 -07:00
Eddie Hung
33862d0445
WIP for fixing partitioning, temporarily do not partition
2019-07-11 09:22:52 -07:00
Eddie Hung
c0abd18799
Enable &mfs for abc9, even if it only currently works for ice40
2019-07-11 08:49:06 -07:00
Eddie Hung
9f608d6be3
write_verilog with *.v extension
2019-07-10 20:25:59 -07:00
Eddie Hung
71acd3ddcf
Remove -retime from abc9, revert to abc behav with separate clock/en domains
2019-07-10 18:57:44 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
whitequark
ea447220da
attrmap: also consider process, switch and case attributes.
2019-07-10 12:30:53 +00:00
Eddie Hung
c2db70f41e
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 12:14:00 -07:00
Eddie Hung
b5072256f2
Update muxcover doc as per @ZirconiumX
2019-07-08 12:50:59 -07:00
Eddie Hung
3681162c8d
atoi -> stoi
2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7
Add muxcover -mux2=cost option
2019-07-08 10:59:12 -07:00
Eddie Hung
ef757002db
Also remove $__ABC_FF_
2019-07-01 10:55:24 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Gabriel L. Somlo
8cb3655ecd
Make abc9 pass aware of optional ABCEXTERNAL override
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-28 14:56:16 -04:00
Eddie Hung
4a2a93aa06
Fix spacing
2019-06-28 11:10:36 -07:00
Eddie Hung
a625854ac5
Do not use Module::remove() iterator version
2019-06-27 15:29:20 -07:00
Eddie Hung
137c91d9a9
Remove &retime when abc9 -fast
2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546
Cleanup abc9.cc
2019-06-27 15:15:56 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
c226af3f56
Fix spacing
2019-06-26 20:03:34 -07:00
Eddie Hung
26efd6f0a9
Support more than one port in the abc_scc_break attr
2019-06-26 19:57:54 -07:00
Eddie Hung
d2fed0a7f1
nullptr check
2019-06-25 06:06:32 -07:00
Eddie Hung
a19226c174
Fix for abc_scc_break is bus
2019-06-24 22:16:56 -07:00
Eddie Hung
5605002d8a
More meaningful error message
2019-06-24 22:12:55 -07:00
Eddie Hung
babadf5938
Do not use log_id as it strips \\, also fix scc for |wire| > 1
2019-06-24 22:04:22 -07:00
Eddie Hung
49a762ba46
Fix abc9's scc breaker, also break on abc_scc_break attr
2019-06-24 21:53:18 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
ad296d77ab
Do not rename non LUT cells in abc9
2019-06-21 17:18:04 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
...
Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Clifford Wolf
ec979475e7
Replace "muxcover -freedecode" with "muxcover -dmux=cost"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 19:24:41 +02:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
...
Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
9286b6f013
Add "muxcover -freedecode"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 10:02:10 +02:00
Eddie Hung
54f3237720
Fix gcc warning of potentially uninitialised
2019-06-20 22:10:43 -07:00
Clifford Wolf
891ea6512e
Improvements in muxcover
...
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
2019-06-20 19:47:59 -07:00
Clifford Wolf
40188457d1
Add support for partial matches to muxcover, fixes #1091
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 19:47:59 -07:00
Eddie Hung
0e97e6a00d
Fix simple_abc9/generate test with 1'bx at MSB
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
3f34779d64
Do not call "setundef -zero" in abc9
2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef
Actually, there might not be any harm in updating sigmap...
2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c
Add comment as per @cliffordwolf
2019-06-20 16:57:54 -07:00
Clifford Wolf
06eb87bcb7
Improve shregmap help message, fixes #1113
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:23:55 +02:00
Eddie Hung
96ade54993
Fix bug in #1078 , add entry to CHANGELOG
2019-06-19 09:51:11 -07:00
Eddie Hung
d80678e581
Cleanup
2019-06-17 15:10:33 -07:00
Eddie Hung
3ebba74461
Merge branch 'xaig' into xaig_dff
2019-06-17 13:51:53 -07:00
Eddie Hung
4d6d593fe3
&scorr before &sweep, remove &retime as recommended
2019-06-17 13:32:08 -07:00
Eddie Hung
a474fe937b
Merge branch 'xaig' into xaig_dff
2019-06-17 13:20:19 -07:00
Eddie Hung
63fc879a5f
Copy not move parameters/attributes
2019-06-17 13:19:45 -07:00
Eddie Hung
7dd3a7f161
Merge branch 'xaig' into xaig_dff
2019-06-17 12:58:41 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
7250c57c5a
Re-enable &dc2
2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3ed95dae8d
Cleanup
2019-06-15 22:48:16 -07:00
Eddie Hung
416312b9ed
abc9 to recover_init by default
2019-06-15 22:44:45 -07:00
Eddie Hung
2309459605
Do not treat $__ABC_FF_ as a user cell
2019-06-15 19:36:55 -07:00
Eddie Hung
cdfb634977
Cleanup
2019-06-15 18:18:56 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
da487c4f31
For now, short $_DFF_[NP]_ from ff_map.v at re-integration
2019-06-15 09:08:18 -07:00
Eddie Hung
2d85725604
Get rid of compiler warnings
2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b
Update abc9 -D doc
2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b
Enable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e
Remove extra semicolon
2019-06-14 10:11:34 -07:00
David Shah
9566573054
ecp5: Add abc9 option
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Eddie Hung
2c40b66785
Rip out all non FPGA stuff from abc9
2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8
Fix spelling
2019-06-12 16:52:09 -07:00
Eddie Hung
b3faf0246d
Be more precise when connecting during ABC9 re-integration
2019-06-12 16:04:33 -07:00
Eddie Hung
2e7e73f483
Remove hacky wideports_split from abc9
2019-06-12 15:52:49 -07:00
Eddie Hung
d9974b85e7
Fix compile errors when #if 1 for debug
2019-06-12 15:47:39 -07:00
Eddie Hung
8bb67fa67c
Do not call abc9 if no outputs
2019-06-12 10:18:44 -07:00
Eddie Hung
14e870d4c4
More write_xaiger cleanup
2019-06-12 10:00:57 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
b2c72f74f0
Merge branch 'xc7mux' into xaig
2019-06-12 09:14:27 -07:00
Eddie Hung
afd620fd5f
Typo: wire delay is -W argument
2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
...
This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
...
This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
6cdea93724
Revert "Try way that doesn't involve creating a new wire"
...
This reverts commit 2f427acc9e
.
2019-06-11 16:05:42 -07:00
Eddie Hung
d26646051c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
...
This reverts commit 5174082208
, reversing
changes made to 54379f9872
.
2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-11 15:48:41 -07:00
Eddie Hung
2f427acc9e
Try way that doesn't involve creating a new wire
2019-06-11 15:48:20 -07:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
f19aa8d989
If d_bit already in sigbit_chain_next, create extra wire
2019-06-10 16:16:40 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
...
This reverts commit 94a5f4e609
.
2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431
Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
...
This reverts commit 45d1bdf83a
.
2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193
Revert "Refactor to ShregmapTechXilinx7Static"
...
This reverts commit e1e37db860
.
2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4
Revert "Add -tech xilinx_static"
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This reverts commit dfe9d95579
.
2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004
Revert "Continue support for ShregmapTechXilinx7Static"
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This reverts commit 72eda94a66
.
2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e
Revert "shregmap -tech xilinx_static to handle INIT"
...
This reverts commit 935df3569b
.
2019-06-10 14:34:12 -07:00
Eddie Hung
5a46a0b385
Fine tune aigerparse
2019-06-07 16:57:32 -07:00
Eddie Hung
30abdaf3b2
Allow muxcover costs to be changed
2019-06-07 08:34:11 -07:00
Eddie Hung
fe4394fb9a
Allow muxcover costs to be changed
2019-06-07 08:30:39 -07:00
Eddie Hung
eaee250a6e
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
2019-06-06 14:06:59 -07:00
Eddie Hung
83450a9489
Move muxpack from passes/techmap to passes/opt
2019-06-06 12:15:13 -07:00
Eddie Hung
3dd0682f29
Update doc
2019-06-06 12:11:59 -07:00
Eddie Hung
3e76e3a6fa
Add tests, fix for !=
2019-06-06 11:54:38 -07:00
Eddie Hung
543dd11c7e
Missing file
2019-06-06 11:03:45 -07:00
Eddie Hung
7bd1c664a6
Initial adaptation of muxpack from shregmap
2019-06-06 10:51:02 -07:00
Eddie Hung
fd8ef128bf
Missing doc for -tech xilinx in shregmap
2019-06-05 14:21:44 -07:00
Eddie Hung
935df3569b
shregmap -tech xilinx_static to handle INIT
2019-06-05 12:55:59 -07:00
Eddie Hung
72eda94a66
Continue support for ShregmapTechXilinx7Static
2019-06-05 12:33:55 -07:00
Eddie Hung
dfe9d95579
Add -tech xilinx_static
2019-06-05 11:14:14 -07:00
Eddie Hung
e1e37db860
Refactor to ShregmapTechXilinx7Static
2019-06-05 11:08:08 -07:00
Eddie Hung
45d1bdf83a
shregmap -tech xilinx_dynamic to work -params and -enpol
2019-06-05 10:21:57 -07:00
Eddie Hung
94a5f4e609
Rename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 14:34:36 -07:00
Eddie Hung
295bd8d0bf
Remove dupe
2019-06-03 12:32:20 -07:00
Eddie Hung
eb08e71bd1
Merge branch 'xaig' into xc7mux
2019-05-31 13:03:03 -07:00
Eddie Hung
a379234f56
Throw out unused code inherited from abc
2019-05-31 12:50:11 -07:00
Eddie Hung
4a6b9af227
Fix spelling
2019-05-30 15:50:47 -07:00
Eddie Hung
a44fe3a632
Revert "Re-enable &dc2"
...
This reverts commit 8c58c728a7
.
2019-05-30 11:41:50 -07:00
Eddie Hung
0800846e73
Do not double count LUT1s
2019-05-30 11:32:14 -07:00
Eddie Hung
8c58c728a7
Re-enable &dc2
2019-05-30 00:42:41 -07:00
Eddie Hung
2560f92f29
Reduce -W to 160
2019-05-29 23:01:46 -07:00
Eddie Hung
854557814e
Erase all boxes before stitching
2019-05-29 19:17:36 -07:00
Eddie Hung
b955344ecd
Call &if with -W 250
2019-05-29 16:34:52 -07:00
Eddie Hung
ecaa7856e9
Add some debug to abc9
2019-05-29 15:21:41 -07:00
Eddie Hung
4a76b425cc
Misspell
2019-05-28 08:44:59 -07:00
Eddie Hung
89bd6b8504
If driver not found, use LUT2
2019-05-27 23:12:21 -07:00
Eddie Hung
4df37c77fd
Disconnect all ABC boxes too
2019-05-27 19:40:27 -07:00
Eddie Hung
75bd41eaeb
Parse without wideports
2019-05-27 12:22:05 -07:00
Eddie Hung
bf3b8d5e45
Remove mapped_mod when done
2019-05-27 12:19:21 -07:00
Eddie Hung
234156c01a
Instantiate cell type (from sym file) otherwise 'clean' warnings
2019-05-27 12:16:10 -07:00
Eddie Hung
03b289a851
Add 'cinput' and 'coutput' to symbols file for boxes
2019-05-27 11:38:52 -07:00
Eddie Hung
3981eba999
ABC9 to call &sweep
2019-05-26 11:31:35 -07:00
Eddie Hung
086b6560b4
Typo
2019-05-26 03:17:20 -07:00
Eddie Hung
823153e418
Combine ABC_COMMAND_LUT
2019-05-26 02:47:06 -07:00
Eddie Hung
32a4c10c0d
Fix "a" extension
2019-05-26 02:44:36 -07:00
Eddie Hung
6ad09bfcea
Add &fraig and &mfs back
2019-05-24 15:10:18 -07:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Henner Zeller
5e443a5d0d
Fix two instances of integer-assignment to string.
...
o In cover.cc, the int-result of mkstemps() was assigned to a string
and silently interpreted as a single-character filename with a funny
value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
visible constructors, this is ambiguous. Explicitly cast this to
a char.
2019-05-14 22:01:15 -07:00
Makai Mann
2f5cfa014b
Zinit option '-singleton' -> '-all'
2019-05-10 10:23:14 -07:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
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Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
David Shah
a84256aa36
abc: Fix handling of postfixed names (e.g. for retiming)
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:23:44 +01:00
David Shah
5ce9113eda
abc: Improve name recovery
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 16:53:25 +01:00
Eddie Hung
e08df0c739
If init is 1'bx, do not add to dict as per @cliffordwolf
2019-05-03 08:06:16 -07:00
Eddie Hung
fc349de033
Revert "dffinit -noreinit to silently continue when init value is 1'bx"
...
This reverts commit aa081f83c7
.
2019-05-03 08:05:37 -07:00
Eddie Hung
aa081f83c7
dffinit -noreinit to silently continue when init value is 1'bx
2019-05-02 17:40:39 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Eddie Hung
acafcdc94d
Copy with 1'bx padding in $shiftx
2019-04-28 13:04:34 -07:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Eddie Hung
4df4a97ffa
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-04-22 18:20:39 -07:00
Eddie Hung
0bd2bfa737
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 18:15:28 -07:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl
...
synth_xilinx to now infer SRL16E/SRLC32E
2019-04-22 13:31:30 -07:00
Eddie Hung
4cfef7897f
Merge branch 'xaig' into xc7mux
2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug
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Add log_debug() framework
2019-04-22 20:09:51 +02:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
e158ea2097
Add log_debug() framework
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
whitequark
aeeefc32d8
attrmap: extend -remove to allow removing attributes with any value.
...
Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
2019-04-22 14:18:15 +00:00
Eddie Hung
d06d4f35c3
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 18:10:46 -07:00
Clifford Wolf
7b35d57592
Disable blackbox detection in techmap files
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 02:07:36 +02:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Eddie Hung
9dc11cd842
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 17:24:06 -07:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox
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[WIP] Add "whitebox" attribute, add "read_verilog -wb"
2019-04-20 20:51:54 +02:00
Eddie Hung
b25254020c
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl
2019-04-20 10:44:01 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Clifford Wolf
f3ad8d680a
Add "techmap -wb", use in formal flows
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:23:24 +02:00
Clifford Wolf
b7445ef387
Check blackbox attribute in techmap/simplemap
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:10:05 +02:00
Eddie Hung
9dec3d9978
Spelling fixes
2019-04-19 14:00:22 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
070a2d2fd6
Fix abc's remap_name to not ignore [^0-9] when extracting sid
2019-04-18 09:55:03 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Eddie Hung
9aa94370a5
ABC to call retime all the time
2019-04-18 08:46:41 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
a20ed260e1
Skip if abc_box_id earlier
2019-04-17 16:36:03 -07:00
Eddie Hung
abcd3103ff
Do not print slack histogram
2019-04-17 15:11:14 -07:00
Eddie Hung
fd89c1056e
Working ABC9 script
2019-04-17 12:33:32 -07:00
Eddie Hung
ae2653c50f
abc9 to output some more info
2019-04-16 16:39:16 -07:00
Eddie Hung
55a3638c71
Port from xc7mux branch
2019-04-16 15:01:45 -07:00
Eddie Hung
fc5fda595d
Merge branch 'xaig' into xc7mux
2019-04-16 13:15:53 -07:00
Eddie Hung
afcb86c3d1
abc9 to call "setundef -zero" behaving as for abc
2019-04-16 13:10:13 -07:00
Eddie Hung
98c297fabf
ABC to read_box before reading netlist
2019-04-16 12:44:10 -07:00
Eddie Hung
a2b106135b
Do not call abc on modules with abc_box_id attr
2019-04-16 11:19:42 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Eddie Hung
9bfcd80063
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
2019-04-12 18:21:16 -07:00
Eddie Hung
482a60825b
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
2019-04-12 18:16:50 -07:00
Eddie Hung
88d43a519b
Use -map instead of -symbols for aiger
2019-04-12 16:29:14 -07:00
Eddie Hung
941365b4bb
Comment out
2019-04-12 12:29:04 -07:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
3c1f1a6605
Fix ordering of when to insert zero index
2019-04-11 16:25:59 -07:00
Eddie Hung
53513c52df
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:21:01 -07:00
Eddie Hung
f587950bde
More unused
2019-04-11 16:20:43 -07:00
Eddie Hung
35181a7866
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
2019-04-11 16:18:45 -07:00
Eddie Hung
b15b410b41
Remove unused
2019-04-11 16:18:01 -07:00
Eddie Hung
b1f1db2fcf
Fixes
2019-04-11 16:17:09 -07:00
Eddie Hung
e8c26f2839
WIP
2019-04-11 15:52:04 -07:00
Eddie Hung
09e7eb7aed
Spelling fixes
2019-04-11 15:09:13 -07:00
Eddie Hung
5f4024ffd2
Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
...
This reverts commit 19271bd996
.
2019-04-10 08:31:40 -07:00
Eddie Hung
78d35a86c0
Revert ""&nf -D 0" fails => use "-D 1" instead"
...
This reverts commit 3c253818ca
.
2019-04-10 08:31:35 -07:00
Eddie Hung
d536379c62
Add "-lut <file>" support to abc9
2019-04-09 14:31:31 -07:00
Eddie Hung
7e304c362b
Add "-box" option to abc9
2019-04-09 10:58:06 -07:00
Eddie Hung
bd523abef5
Add 'setundef -zero' call prior to aigmap in abc9
2019-04-09 10:32:58 -07:00
Eddie Hung
3b6f85b0a6
Comment out
2019-04-09 10:09:43 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Eddie Hung
12c34136ba
More space fixing
2019-04-08 16:40:17 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
6797f6b6c4
$_XILINX_SHREG_ to preserve src attribute
2019-04-08 16:24:20 -07:00
Eddie Hung
93b1621911
Cope with undoing #895
2019-04-08 15:57:07 -07:00
Eddie Hung
d3930ca79e
Revert "Remove handling for $pmux, since #895"
...
This reverts commit aa693d5723
.
2019-04-08 12:01:06 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
4afcad70e2
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 16:30:17 -07:00
Eddie Hung
d559023007
Fix S0 -> S1
2019-04-05 16:28:14 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
3c253818ca
"&nf -D 0" fails => use "-D 1" instead
2019-04-05 15:30:19 -07:00
Eddie Hung
19271bd996
abc -dff now implies "-D 0" otherwise retiming doesn't happen
2019-04-05 14:42:25 -07:00
Eddie Hung
aa693d5723
Remove handling for $pmux, since #895
2019-04-03 08:35:32 -07:00
Eddie Hung
d8465590ac
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 03:36:11 -07:00
Niels Moseley
263ab60b43
Liberty file parser now accepts superfluous ;
2019-03-27 15:17:58 +01:00
Niels Moseley
487cb45b87
Liberty file parser now accepts superfluous ;
2019-03-27 15:15:53 +01:00
Eddie Hung
6b90d3cf6c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-25 13:17:22 -07:00
Niels Moseley
1f7f54e68e
spaces -> tabs
2019-03-25 14:12:04 +01:00
Niels Moseley
9d9cc8a314
EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)
2019-03-25 12:15:10 +01:00
Niels Moseley
3b3b77291a
Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
2019-03-24 22:54:18 +01:00
Eddie Hung
bf83c074c8
Cope with SHREG not having E port; Revert $pmux fine tune
2019-03-23 16:09:38 -07:00
Eddie Hung
098bd5758f
Add support for SHREGMAP+$mux, also fine tune $pmux
2019-03-22 23:22:19 -07:00
Eddie Hung
0895093c7c
Leftover printf
2019-03-22 19:14:04 -07:00
Eddie Hung
456295eb66
Fixes for multibit
2019-03-22 18:32:42 -07:00
Eddie Hung
03d108cd1f
Working for 1 bit
2019-03-22 17:46:49 -07:00
Eddie Hung
5597270b9e
Opt
2019-03-21 10:20:27 -07:00
Eddie Hung
2b911e270b
Fix spacing
2019-03-20 12:28:39 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
4cd8f02973
shregmap -tech xilinx to delete $shiftx for var length SRL
2019-03-19 15:05:08 -07:00
Eddie Hung
0ea7eba5f1
Make output port a non chain user
2019-03-19 13:08:43 -07:00
Eddie Hung
ed32119d13
Fix shregmap to correctly recognise non chain users; cleanup
2019-03-18 16:12:19 -07:00
Eddie Hung
b94db54664
shiftx NULL pointer check
2019-03-18 13:35:54 -07:00
Eddie Hung
d6d9ef0fee
Cleanup
2019-03-16 12:49:46 -07:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
7cac3b1c8b
abc9 -- multiple connections for inouts
2019-02-26 12:18:28 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57
abc9 cleanup
2019-02-25 18:40:53 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c
abc9 not to clean after aigmap
2019-02-25 15:31:52 -08:00
Eddie Hung
51f28a6747
abc9 to call "clean" once at the end of all abc9_module() calls
2019-02-25 12:55:47 -08:00
Eddie Hung
d56f02d1fc
abc9 to use AIGER symbol table, as opposed to map file
2019-02-21 17:03:40 -08:00
Eddie Hung
2811d66dea
Revert "abc9 to write_xaiger -symbols, not -map"
...
This reverts commit 04429f8152
.
2019-02-21 14:58:40 -08:00
Eddie Hung
7ad9628f07
Remove irrelevant citations
2019-02-21 14:41:11 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
875a02a6f2
abc9 to not select anything extra, and pop selection after final clean
2019-02-21 14:38:52 -08:00
Eddie Hung
04429f8152
abc9 to write_xaiger -symbols, not -map
2019-02-21 14:28:36 -08:00
Eddie Hung
3307295488
Merge branch 'read_aiger' into xaig
2019-02-21 14:27:32 -08:00
Eddie Hung
7f8f36273a
abc9 to use &mfs
2019-02-21 13:16:24 -08:00
Eddie Hung
6b96df41bc
abc9 to only disconnect output ports of AND and NOT gates
2019-02-21 11:15:47 -08:00
Eddie Hung
7f26043caf
ABC -> ABC9
2019-02-20 17:36:57 -08:00
Eddie Hung
e5b8bb9faa
abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_
2019-02-20 17:33:35 -08:00
Eddie Hung
32853b1f8d
lut/not/and suffix to be ${lut,not,and}
2019-02-20 16:30:30 -08:00
Eddie Hung
2ca83005fb
abc9 to cope with multiple modules
2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349
abc9 to use & syntax for -fast, and name fixes
2019-02-20 12:40:17 -08:00
Eddie Hung
62e5ff9ba8
abc9 to cope with indexed wires when creating $lut from $_NOT_
2019-02-19 16:06:03 -08:00
Eddie Hung
8158bc3f99
abc9 to replace $_NOT_ with $lut
2019-02-19 12:30:20 -08:00
Eddie Hung
45d49d5d14
Get rid of debugging stuff in abc9
2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1
abc9 to write_aiger with -O option, and ignore dummy outputs
2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire
2019-02-16 13:47:38 -08:00
Eddie Hung
d4545d415b
abc9 to cope with non-wideports, count cells properly
2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598
Move lookup inside if
2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53
Refactor
2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9
Cope with width != 1 when re-mapping cells
2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5
abc9 to stitch results with CI/CO properly
2019-02-15 11:52:34 -08:00
Eddie Hung
206f11dca3
Fix stitching
2019-02-13 17:04:23 -08:00
Eddie Hung
f0f5d8a5cc
Merge remote-tracking branch 'origin/read_aiger' into xaig
2019-02-13 14:09:36 -08:00
Eddie Hung
87f059adf7
Rip out some more stuff
2019-02-13 10:44:52 -08:00
Eddie Hung
045f7763ae
Rip out unused functions in abc9
2019-02-12 16:25:22 -08:00
Eddie Hung
b3341b4abb
WIP for ABC with aiger
2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751
Missing headers for Xcode?
2019-02-12 09:24:13 -08:00
Eddie Hung
5a0a5aae4f
Compile abc9
2019-02-08 13:58:47 -08:00
Eddie Hung
e25a22015f
Copy abc.cc to abc9.cc
2019-02-08 13:23:54 -08:00
David Shah
58c22dae31
abc: Improved recovered netnames, also preserve src on nets with dress
...
Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
8524a479b1
abc: Preserve naming through ABC using 'dress' command
...
Signed-off-by: David Shah <dave@ds0.me>
2019-02-06 22:23:13 +01:00
whitequark
e792bd56b7
flowmap: clean up terminology.
...
* "map": group gates into LUTs;
* "pack": replace gates with LUTs.
This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.
Also clean up some other log messages while we're at it.
2019-01-08 02:05:06 +00:00
whitequark
211c26a4c9
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
whitequark
8b44198e23
flowmap: construct a max-volume max-flow min-cut, not just any one.
2019-01-06 19:51:37 +00:00
whitequark
2fcc1ee72e
flowmap: add -minlut option, to allow postprocessing with opt_lut.
2019-01-04 21:18:03 +00:00
whitequark
9bc5cf0844
flowmap: cleanup for clarity. NFCI.
2019-01-04 13:04:20 +00:00
whitequark
fd21564deb
flowmap: improve debug graph output. NFC.
2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a
flowmap: add link to longer version of paper. NFC.
2019-01-04 02:33:10 +00:00
whitequark
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
Icenowy Zheng
256fb8c95c
Add "dffinit -noreinit" parameter
...
Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Icenowy Zheng
fec8b3c81f
Add "dffinit -strinit high low"
...
On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
Clifford Wolf
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
...
deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
...
Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
...
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
Clifford Wolf
c800e3bb16
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-04 23:30:23 +01:00
Sylvain Munaut
8d3ab626ea
dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Niels Moseley
cfc9b9147c
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696
Liberty file newline handling is more relaxed. More descriptive error message
2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a
Report an error when a liberty file contains pin references that reference non-existing pins
2018-11-03 18:07:51 +01:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
...
Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Robert Ou
9763e4d830
Fix infinite loop in abc command under emscripten
2018-05-18 22:42:39 -07:00
Robert Ou
bfce3a7479
Add an option to statically link abc into yosys
...
This is currently incomplete because the output filter no longer works.
2018-05-18 22:35:28 -07:00
Clifford Wolf
fe80b39f56
Fix iopadmap for loops between tristate IO buffers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c
Fix iopadmap for cases where IO pins already have buffers on them
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 13:13:43 +02:00
Clifford Wolf
145c685de0
Add ABC FAQ to "help abc"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91
Added missing dont_use handling for SR FFs to dfflibmap
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-05 11:01:45 +02:00
Clifford Wolf
a74f805ba0
Fix handling of src attributes in flatten
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 13:55:30 +01:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Staf Verhaegen
92eb841f0a
Value of properties can be expression.
...
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
2018-01-03 21:37:17 +00:00
Clifford Wolf
7c57d8fbb4
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c
Implemented off-chain support for extract_reduce
2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
2017-09-15 13:59:05 -07:00
Clifford Wolf
ce78717e36
Merge pull request #412 from azonenberg/reduce-fixes
...
extract_reduce: Fix segfault on "undriven" inputs
2017-09-14 22:36:25 +02:00
Robert Ou
ab1bf8d661
extract_reduce: Fix segfault on "undriven" inputs
...
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
2017-09-14 12:54:44 -07:00
Andrew Zonenberg
367d6b2194
Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output
2017-09-14 10:27:10 -07:00
Andrew Zonenberg
c8f2f082c6
Added support for inferring counters with reset to full scale instead of zero
2017-09-14 10:26:43 -07:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
0484ad666d
Added support for inferring counters with active-low reset
2017-09-14 10:26:21 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Andrew Zonenberg
c4a70a8cc3
Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
2017-09-14 10:25:51 -07:00
Clifford Wolf
7d41c5e177
Further improve extract_fa (but still buggy)
2017-09-02 16:39:17 +02:00
Clifford Wolf
18609f3df8
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 12:35:09 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
8dc6083de7
updated to use get_src_attribute() and set_src_attribute().
2017-08-31 14:51:56 -06:00
Andrew Zonenberg
ed1e3ed39b
extract_counter: Added optimizations to remove unused high-order bits
2017-08-30 18:15:12 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Jason Lowdermilk
32c0f1193e
Add support for source line tracking through synthesis phase
2017-08-29 14:46:35 -06:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
46b01f05bb
Refactored extract_counter to be generic vs GreenPAK specific
2017-08-28 22:18:47 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Clifford Wolf
908f34aafc
Rename recover_reduce to extract_reduce, fix args handling
2017-08-28 19:52:06 +02:00
Clifford Wolf
3aad3ed3da
Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce
2017-08-28 19:46:17 +02:00
Clifford Wolf
ebbb0e9479
Further improve extract_fa pass
2017-08-28 19:43:26 +02:00
Robert Ou
849b885775
recover_reduce: Update documentation
...
The documentation now describes the commands performed in the deleted
recover_reduce script.
2017-08-27 02:19:19 -07:00
Robert Ou
74d0f17fd4
recover_reduce: Reindent using tabs
2017-08-27 02:12:41 -07:00
Robert Ou
8a5887464c
recover_reduce: Rename recover_reduce_core to recover_reduce
...
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.
Also rename to .cc (rather than .cpp) for consistency.
2017-08-27 02:01:32 -07:00
Robert Ou
99dad40ed0
recover_reduce: Add driver script for the $reduce_* recover feature
...
Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:57:20 -07:00
Robert Ou
8b7dc792ee
recover_reduce_core: Finish implementing the core function
2017-08-27 01:56:49 -07:00
Robert Ou
fa310c98f8
recover_reduce_core: Initial commit
...
Conflicts:
passes/techmap/Makefile.inc
2017-08-27 01:56:49 -07:00
Clifford Wolf
382cc90c65
Further improve extract_fa (seems to be fully functional now)
2017-08-25 13:41:54 +02:00
Clifford Wolf
0bf612506c
Rename "adders" to "extract_fa"
2017-08-25 12:04:40 +02:00
Clifford Wolf
15cdda7c4b
Towards more generic "adder" function extractor
2017-08-23 14:20:10 +02:00
Clifford Wolf
51cbec7f75
Add experimental adders pass
2017-08-22 13:52:13 +02:00
Robert Ou
9a64ba3338
abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
Clifford Wolf
5c09f24e48
Fix typo in "abc" pass help message
2017-07-29 16:21:58 +02:00
Clifford Wolf
b3bc7068d1
Fix handling of empty cell port assignments (i.e. ignore them)
2017-07-21 19:32:31 +02:00
Clifford Wolf
155a80dfb7
Fix handling of init values in "abc -dff" and "abc -clk"
2017-06-20 15:32:23 +02:00
Clifford Wolf
f6421c83a2
Switched abc "clock domain not found" error to log_cmd_error()
2017-06-20 04:22:34 +02:00
Clifford Wolf
fad52abf70
Add aliases for common sets of gate types to "abc -g"
2017-05-24 11:39:05 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
Clifford Wolf
db7314bc02
Fix techmap for inout ports connected to inout ports
2017-02-13 16:55:25 +01:00
Clifford Wolf
8927e19b13
Update ABC scripts to use "&nf" instead of "map"
2017-02-01 11:15:20 +01:00
Clifford Wolf
55785a96eb
Improved ABC default scripts
2016-11-19 18:20:54 +01:00
Clifford Wolf
74702b04c2
Build fixes for VS 2015
2016-10-16 20:37:02 +02:00
Clifford Wolf
e4c5ee9b89
Avoid using strcasecmp()
2016-10-14 18:20:36 +02:00
Clifford Wolf
ffbb4e992e
Added MEMID handling to "flatten" pass
2016-10-14 10:36:37 +02:00
Clifford Wolf
ee91350add
Added "zinit" pass
2016-10-12 12:05:19 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
d8ad889594
Bugfix in techmap parameter handling
2016-09-14 20:46:54 +02:00
Clifford Wolf
73b7232ec8
Fixed some compiler warnings in attrmap command
2016-08-10 13:44:08 +02:00
Clifford Wolf
b0aab4e304
Added "attrmap" command
2016-08-09 19:56:55 +02:00
Clifford Wolf
3c6d31fd06
Added "attrmvcp" pass
2016-08-09 11:18:48 +02:00
Clifford Wolf
9d15529214
Undo "preserve wire attributes in iopadmap" change (it was OK before)
2016-08-08 11:47:35 +02:00
Clifford Wolf
90c17aad56
preserve wire attributes in iopadmap
2016-08-06 13:24:59 +02:00
Clifford Wolf
5d6765a9d2
Added "insbuf" command
2016-08-02 10:37:19 +02:00
Clifford Wolf
541083cf32
Bugfix in "abc -script" handling
2016-06-19 22:19:19 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
3380281e15
Added "dc2" to default ABC scripts
2016-06-17 20:15:35 +02:00
Clifford Wolf
f498204ae4
Added "abc -I <num> -P <num>"
2016-06-17 19:39:35 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
c3365034e9
Updated ABC to hg rev b5df6e2b76f0
2016-06-17 11:16:31 +02:00
Clifford Wolf
99edf24966
Added "nlutmap -assert"
2016-06-09 11:47:41 +02:00
Clifford Wolf
c3f6e0ea85
Added support for "keep" attribute to shregmap
2016-05-07 09:33:16 +02:00
Clifford Wolf
aadca148da
Fixed preservation of important attributes in techmap
2016-05-06 13:59:30 +02:00
Andrew Zonenberg
3486637b19
Changed port names in greenpak shregmap
2016-05-04 17:04:50 -07:00
Clifford Wolf
9647dc3c07
Added tristate buffer support to iopadmap
2016-05-04 22:48:02 +02:00
Clifford Wolf
658f93663b
Fixed iopadmap attribute handling
2016-05-04 10:48:23 +02:00
Clifford Wolf
096c25d29d
Improvements in greenpak4 shreg mapping
2016-04-23 23:10:13 +02:00
Andrew Zonenberg
7f16784f3c
Merge https://github.com/cliffordwolf/yosys
2016-04-23 12:22:08 -07:00
Clifford Wolf
e13c66122e
Added "shregmap -zinit" for greenpak4 tech
2016-04-23 20:20:21 +02:00
Andrew Zonenberg
2849fd486e
Fixed typo in help text
2016-04-22 23:01:39 -07:00
Clifford Wolf
7311be4028
Added "shregmap -tech greenpak4"
2016-04-22 19:42:08 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
f1fa757d0e
Added "shregmap -params"
2016-04-18 11:58:21 +02:00
Clifford Wolf
525651c8f6
Added "shregmap -zinit" and "shregmap -init"
2016-04-18 11:44:10 +02:00
Clifford Wolf
ce7c980ec7
Improvements in "shregmap"
2016-04-17 15:37:22 +02:00
Clifford Wolf
de647a390c
Added "shregmap" pass
2016-04-16 23:20:49 +02:00
Clifford Wolf
fbdb8e7b3e
Fixed copy&paste error in log message in lut2mux
2016-04-16 23:20:34 +02:00
Clifford Wolf
6041f780c3
Prefer noninverting FFs in dfflibmap
2016-04-05 12:51:04 +02:00
Clifford Wolf
9717495401
Fixed handling of inverters (aka 1-input luts) in nlutmap
2016-03-23 08:56:08 +01:00
Clifford Wolf
bb9374b67c
Improvements in ABCEXTERNAL handling
2016-03-19 20:02:40 +01:00
Sergey Kvachonok
2656b2c55a
Support calling out to an external ABC.
...
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install
configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
2016-03-19 18:36:18 +03:00
Clifford Wolf
c4aaed099f
Using "mfs" and "lutpack" in ABC lut mapping
2016-03-07 11:14:11 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
801c022457
Improved dffsr2dff pass
2016-02-02 19:42:49 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
9251553592
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)
2016-02-01 11:49:11 +01:00
Clifford Wolf
71f418c468
More clang sanitizer stuff
2016-01-31 19:55:48 +01:00
Clifford Wolf
d98d99aec6
Added "abc -g"
2015-11-10 11:10:11 +01:00
Marcus Comstedt
8c2bdef36d
Fix a segfault in dffinit when the value has too few bits
...
The code was already trying to add the required number of bits, but
fell one short of the mark.
2015-11-08 19:16:56 +01:00
Clifford Wolf
f401eeb0cf
Bugfix in mapping $tribuf to $_TBUF_
2015-11-05 12:37:43 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
6fe48cf41e
equiv_purge bugfix, using SigChunk in Yosys namespace
2015-10-24 19:09:45 +02:00
Clifford Wolf
eb1e3caae7
Fixed "flatten" for unconnected inout ports
2015-10-13 10:30:23 +02:00
Clifford Wolf
598a475724
Added nlutmap
2015-09-18 21:57:34 +02:00
Clifford Wolf
c851f51656
Added lut2mux pass
2015-09-18 21:55:48 +02:00
Clifford Wolf
db548800b6
Added buffer detection to "abc -lut"
2015-09-18 20:12:56 +02:00
Clifford Wolf
452d4bf741
Added support for "dfflibmap -liberty +/..."
2015-09-18 11:55:57 +02:00
Clifford Wolf
24e7cf89bc
Fixed iopadmap help message
2015-08-31 16:49:42 +02:00
Clifford Wolf
92dce21f6e
Using dict<> and pool<> in alumacc pass
2015-08-31 16:26:01 +02:00
Clifford Wolf
f43815054e
Properly clean up unused "init" attributes
2015-08-18 13:50:15 +02:00
Clifford Wolf
9c33172ece
Added tribuf command
2015-08-16 12:55:25 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
80910d13a6
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 09:52:06 +02:00
Clifford Wolf
08ad5409a2
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
2015-08-13 09:30:20 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
3860c9a9f2
Fixed flatten $meminit handling
2015-07-30 21:43:41 +02:00
Clifford Wolf
ad919ae4e3
Fixed techmap processes error msg
2015-07-18 12:16:27 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
1ae360cf72
AigMaker refactoring
2015-06-10 23:00:12 +02:00
Clifford Wolf
56d4822719
Renamed "aig" to "aigmap"
2015-06-10 07:24:26 +02:00
Clifford Wolf
85287295b2
Fixed cellaigs port extending
2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a
Added "aig" pass
2015-06-09 22:33:26 +02:00
Clifford Wolf
522705cc28
Added liberty dont_use support to dfflibmap
2015-05-31 07:51:12 +02:00
Clifford Wolf
9f772eb970
Improved "flatten" handlings of inout ports
2015-05-23 10:14:53 +02:00
Clifford Wolf
e5116eeb77
Generalized blifparse API
2015-05-17 15:10:37 +02:00
Clifford Wolf
7dad017c9c
abc/blifparse files reorganization
2015-05-17 14:44:28 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
49859393bb
Improved attributes API and handling of "src" attributes
2015-04-24 22:04:05 +02:00
Clifford Wolf
8cdbcf6859
Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
2015-04-17 21:35:59 +02:00
Clifford Wolf
e050467b89
Improved "maccmap" help message
2015-04-16 18:23:43 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
f80d020f17
Added "dff2dffe -direct-match"
2015-04-16 11:30:17 +02:00
Clifford Wolf
be7b9b34ca
techmap code cleanup
2015-04-09 12:02:26 +02:00
Clifford Wolf
21a1cc1b60
Added support for "file names with blanks"
2015-04-08 12:14:34 +02:00
Clifford Wolf
aa0ab975b9
Removed "techmap -share_map" (use "-map +/filename" instead)
2015-04-08 12:13:53 +02:00
Clifford Wolf
724cead61d
Added "pmuxtree" command
2015-04-07 20:27:10 +02:00
Clifford Wolf
590f74d8f0
Added decoder generation to "muxcover"
2015-04-07 18:03:27 +02:00
Clifford Wolf
f7fb21f185
Added "muxcover" command
2015-04-07 15:42:25 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
8b1e0bdd9e
Fixed handling of quotes in liberty parser
2015-03-18 16:03:19 +01:00
Clifford Wolf
27a918eadf
Merge branch 'master' of github.com:cliffordwolf/yosys
2015-02-25 23:01:54 +01:00
Clifford Wolf
331f8b8d0b
Bugfix in iopadmap
2015-02-25 23:01:42 +01:00
Clifford Wolf
3fe18c26cd
Added "keep_hierarchy" attribute
2015-02-25 12:46:00 +01:00
Clifford Wolf
49dd9c713f
Fixed "flatten" for non-pre-derived modules
2015-02-21 15:01:13 +01:00
Clifford Wolf
f778a4081c
Catch constants assigned to cell outputs in "flatten"
2015-02-21 11:21:28 +01:00
Clifford Wolf
f41378af8c
Fixed clang (svn trunk) warnings
2015-02-18 14:54:22 +01:00
Clifford Wolf
3216f9420e
More emscripten stuff, Added example app
2015-02-15 12:09:30 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
8658eed52a
Added support for memories to flatten (techmap)
2015-01-17 20:46:52 +01:00
Clifford Wolf
8ce8a230f4
Bugfix in dff2dffe
2015-01-16 17:51:17 +01:00
Clifford Wolf
9065fb25cc
Fixed handling of foo.__TECHMAP_...
2015-01-15 13:36:57 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
170788a3de
Fixed simplemap for $ne cells with output width > 1
2014-12-25 16:41:20 +01:00
Clifford Wolf
aad195b88c
Added "dfflibmap -prepare" help
2014-12-24 12:56:05 +01:00
Clifford Wolf
35f5aa300f
Added "dfflibmap -prepare"
2014-12-24 12:19:20 +01:00
Clifford Wolf
032ce573a3
Added "dff2dffe -direct" for direct gate mapping
2014-12-24 11:39:15 +01:00
Clifford Wolf
8c1a72c2a4
Added "dff2dffe -unmap"
2014-12-24 11:09:01 +01:00
Clifford Wolf
afcacd6437
Added support for gate-level cells in dff2dffe
2014-12-24 10:49:54 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
032511fac8
Added functionality to dff2dffe pass
2014-12-08 15:38:58 +01:00
Clifford Wolf
97487fee32
Added skeleton dff2dffe pass
2014-12-08 14:10:52 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
546e8b5fe7
Improved TopoSort determinism
2014-11-07 15:21:03 +01:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
Clifford Wolf
973d376733
Added genfiles.zip to MXE "make dist"
2014-10-17 12:11:15 +02:00
Clifford Wolf
c21c9dab1e
Removed CHECK() macro from libparse.cc (was using non-std c features)
2014-10-13 17:22:06 +02:00
Clifford Wolf
54bf3a95dd
More Win32 build fixes
2014-10-10 18:34:19 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
ccf7b2e342
Added mxe-based cross build for win32
2014-10-09 10:50:44 +02:00
Clifford Wolf
696d7ed40e
Fixes in "hilomap" help message
2014-10-08 21:38:37 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
b86410b2ab
More aggressive $macc merging in alumacc
2014-09-15 12:42:11 +02:00
Clifford Wolf
b470c480e9
Added the obvious optimizations to alumacc $macc generator
2014-09-15 12:22:03 +02:00
Clifford Wolf
fcbda07411
Improved maccmap tree bit packing
2014-09-15 12:00:19 +02:00
Clifford Wolf
7e156a5419
Fixed techmap_wrap for techmap_celltype
2014-09-14 15:34:36 +02:00
Clifford Wolf
014bb34e0e
Various fixes/cleanups in alumacc and maccmap
2014-09-14 14:49:53 +02:00
Clifford Wolf
124e759280
Added techmap_wrap attribute
2014-09-14 14:49:26 +02:00
Clifford Wolf
b34ca15185
alumacc fix for $pos cells
2014-09-14 14:00:14 +02:00
Clifford Wolf
0df1d9ad72
Extract $alu cells in alumacc
2014-09-14 13:23:44 +02:00
Clifford Wolf
7b16c63101
Merge $macc cells in alumacc pass
2014-09-14 11:21:37 +02:00
Clifford Wolf
0b72f0acb1
Basic $macc extract in alumacc
2014-09-14 10:45:28 +02:00
Clifford Wolf
ff157fb74f
alumacc skeleton
2014-09-14 10:02:00 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
1a88e47396
Trim msb/lsb zero bits from full adder in maccmap
2014-09-08 11:21:58 +02:00
Clifford Wolf
c50b841b29
Added 'techmap_maccmap' techmap attribute
2014-09-07 18:23:37 +02:00
Clifford Wolf
015dcdc84c
Added "maccmap" command
2014-09-07 18:23:04 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
826fdb34d8
Added "techmap -autoproc"
2014-09-01 15:36:29 +02:00
Clifford Wolf
d148b0af0d
Fixed inserting of Q-inverters in dfflibmap
2014-08-27 19:44:12 +02:00
Clifford Wolf
c642dd0b3e
Only call proc_share_dirname() in techmap when necessary
2014-08-23 15:32:00 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
410d043dd8
Renamed toposort.h to utils.h
2014-08-17 00:55:35 +02:00
Clifford Wolf
674f421b47
Bugfix in iopadmap
2014-08-15 14:29:42 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
ca87116449
More idstring sort_by_* helpers and fixed tpl ordering in techmap
2014-08-15 02:40:46 +02:00
Clifford Wolf
d320e75087
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
08ec33a5e5
Implemented simplemap support for "techmap -extern"
2014-08-02 21:55:13 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
6ca0c569d9
Added "techmap -assert"
2014-07-31 02:21:41 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
8b0f50792c
Added techmap -extern
2014-07-27 21:31:18 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
49f72421d5
Using new obj iterator API in a few places
2014-07-27 11:32:42 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
3f4e3ca8ad
More RTLIL::Cell API usage cleanups
2014-07-26 16:14:02 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
45b4154b37
Added "make SMALL=1"
2014-07-24 19:03:57 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
b76bf05cda
Added support for "blackbox" attribute to iopadmap
2014-07-17 08:59:07 +02:00
Clifford Wolf
64a6906cc4
Added support for "blackbox" attribute to flatten/techmap
2014-07-17 08:58:51 +02:00